MC88915T Search Results

Contextual Info: Freescale Semiconductor, Inc. Order number: MC88915T Rev 6, 08/2004 TECHNICAL DATA Low Skew CMOS PLL Clock Drivers, 3-State 55, 70, 100, 133, and 160 MHz Versions MC88915TFN55 MC88915TFN70 MC88915TFN100 MC88915TFN133 MC88915TFN160 The MC88915T Clock Driver utilizes phase-locked loop PLL technology to

Motorola D8N

Abstract: MC88915 MC88915T MC88915TFN100 MC88915TFN133 MC88915TFN160 MC88915TFN55 MC88915TFN70 MC88LV915T
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Skew CMOS PLL Clock Drivers, 3-State 55, 70, 100, 133 and 160MHz Versions Order Number: MC88915T/D Rev 5, 08/2001 MC88915TFN55 MC88915TFN70 MC88915TFN100 MC88915TFN133 MC88915TFN160 The MC88915T Clock Driver utilizes phase–locked loop technology to

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low S kew CMOS PLL Clock Drivers, 3 -S ta te 55, 70, 100, 133 and 160MHz Versions The MC88915T Clock Driver utilizes phase-locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference

Contextual Info: MOTOROLA Order this document from Logic Marketing SEMICONDUCTOR TECHNICAL DATA Advance Information Low Skew CMOS PLL Clock Drivers, 3ĆState 55, 70, 100, 133 and 160MHz Versions MC88915TFN55 MC88915TFN70 MC88915TFN100 MC88915TFN133 MC88915TFN160 The MC88915T Clock Driver utilizes phase-locked loop technology to

Contextual Info: Integrated Device Technology, Inc. LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH 3-STATE FEATURES: • • • • • • • • • • • • 0.5 MICRON CMOS Technology Input frequency range: 2.5M Hz - f2Q Max. spec Max. output frequency: 133MHz Pin and function compatible with MC88915T

Contextual Info: MOTOROLA Freescale Semiconductor, Inc. Order Number: MC88915T/D Rev 5, 08/2001 SEMICONDUCTOR TECHNICAL DATA Low Skew CMOS PLL Clock Drivers, 3-State 2 55, 70, 100, 133 and 160MHz Versions MC88915TFN55 MC88915TFN70 MC88915TFN100 MC88915TFN133 MC88915TFN160

Contextual Info: Integrated Device Technology, Inc. LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH 3-STATE FEATURES: • 0.5 MICRON CMOS Technology • Input frequency range: 10MHz - f2Q Max. spec (FREQ_SEL = HIGH) • Max. output frequency: 133MHz • Pin and function com patible with MC88915T

MC68B21CP

Abstract: xcm916x1cth16 transistor marking code 12W SOT-23 sg379 MC68B54P XC68HC805P18CDW mc68b50cp MC2830 NE555N CHN NE555N
Contextual Info: SG379/D REV 7 Semiconductor Products Sector NORTH AMERICA SALES AND DISTRIBUTION PRICE LIST THIS BOOK IS IN COMPUTER SORT PRODUCT CLASSIFICATION – Please see General Information Section 1.3 EFFECTIVE DATE: JANUARY 10, 1998 General Information 1 Cross References

WP-90516-19.66MHZ

Abstract: Mpc601
Contextual Info: MOTOROLA Order this data sheet from Logic Marketing SEMICONDUCTOR TECHNICAL DATA MC88PL117 CMOS PLL Clock Driver Programmable Frequency, Low Skew, High FanĆOut The MC88PL117 utilizes proven phase-locked loop clock driver technology to create a large fan-out, multiple frequency and phase, low

Contextual Info: MOTOROLA Order this document from Logic Marketing SEMICONDUCTOR TECHNICAL DATA Low Voltage Low Skew CMOS PLL Clock Driver, MC88LV915T 3-State The MC88LV915T Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference

CY2305-CY23505

Abstract: PC100SDRAM Advanced Telecommunication Modules mpc940 3 pin crystal oscillator 32 PIN LQFP lvds 32 pin MC100ES6139 motorola ECL Pentium 4 1.5 ghz
Contextual Info: TIMING AND INTERCONNECT SOLUTIONS QUARTER 4, 2003 SG1012/D REV 0 WWW.MOTOROLA.COM/SEMICONDUCTORS About This Revision–Q4/2003 A summary of new information is provided in this section. In addition, a change bar appears in the left margin of every page referenced in this section to mark the

ansi y14.5m-1982 .xxxx

Abstract: diode chn 115
Contextual Info: :nW J d t In te g ra te d D e v ic e T e c h n o lo g y , Inc. 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH 3-STATE) FEATURES: • 0.5 MICRON CMOS Technology • Input frequency range: 10MHz - f2Q Max. spec (F R E Q S E L = HIGH) • Max. output frequency: 150MHz

CHN 530

Abstract: chn 707 hiab chn 445 CHN 455
Contextual Info: :Q§ LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH 3-STATE : jdfr/ Integrated De vice Technology, Inc. FEATURES: IDT74FCT88915TT 55/70/100/133 mance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting in essentially

74FCT388915T

Abstract: FCT388915T MC88915T
Contextual Info: IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH 3-STATE Integrated Device Technology, Inc. IDT54/74FCT388915T 70/100/133/150 PRELIMINARY FEATURES:

FCT388915T

Abstract: IDT74FCT388915T MC88915T 74FCT388915
Contextual Info: IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER 3-STATE COMMERCIAL TEMPERATURE RANGE 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) FEATURES: IDT74FCT388915T 70/100/133/150 DESCRIPTION: • 0.5 MICRON CMOS Technology • Input frequency range: 10MHz – f2Q Max. spec

388915T

Contextual Info: IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER 3-STATE COMMERCIAL TEMPERATURE RANGE 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) IDT74FCT388915T 70/100/133/150 NRND NOT RECOMMENDED FOR NEW DESIGNS FEATURES: DESCRIPTION: • 0.5 MICRON CMOS Technology

MPC9865

Abstract: mpc940 MPC9315 MPC96877 MPC9819 MPC9824 EIA-724 MPC9449
Contextual Info: Timing and Interconnect Solutions Quarter 3, 2005 SG1012Q32005 Rev 0 About This Revision–Q3/2005 When new products are introduced, a summary of the new products will be provided in this section. However, the New Product section will only appear on this page when new

388915T

Abstract: 20PF FCT388915T IDT74FCT388915T MC88915T SO28-7
Contextual Info: IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH 3-STATE IDT74FCT388915T 70/100/133/150 FEATURES: DESCRIPTION: − − The FCT388915T uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low

MC88100

Abstract: motorola 88000 MPC904 TAG 8446 IC Data-book semiconductors cross reference mc6804 mc88913 fuji semi motorola smd transistor code 935
Contextual Info: DATA SHEET CLASSIFICATIONS Product Preview This heading on a data sheet indicates that the device is in the formative stages or in design under development . The disclaimer at the bottom of the first page reads: “This document contains information on a product under development. Motorola reserves the

diode cc 3053

Abstract: cc 3053 diode cc 3053 st074
Contextual Info: In te g ra te d D e v ic e T e c h n o lo g y, In c . LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH 3-STATE FEATURES: • • • • • • • • • • • IDT54/74FCT88915T 55/70/100/133 PRELIMINARY essentially zero delay across the device. The PLL consists of

mpc601

Abstract: PLL 120Mhz 30mhz ceramic FILTER MC88915TFN133 MC88PL117 Nippon capacitors
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Not Recommended for New Designs MC88PL117 CMOS PLL Clock Driver Programmable Frequency, Low Skew, High Fan-Out The MC88PL117 utilizes proven phase–locked loop clock driver technology to create a large fan–out, multiple frequency and phase, low

sn74ls151 multiplexer vhdl code

Abstract: MC14500B MC667 MC14000B MC672 equivalent MC661 MC672 MC660 bounce eliminator mc12073
Contextual Info: Logic: Standard, Special and Programmable In Brief . . . Page Motorola Programmable Arrays MPA . . . . . . . . . . . . 3.1–1 Selection by Function Logic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–8 Device Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1–36

Contextual Info: Integrated Device Technology, Inc. 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH 3-STATE FEATURES: • • • • • • • • • • • • • 0.5 MICRON CMOS Technology Input frequency range: 10MHz - f2Q Max. spec Max. output frequency: 150MHz

t8891

Contextual Info: In te g rate d D e vic e Technology, Inc. LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH 3-STATE IDT54/74FCT88915TT 55/70/100/133 PRELIMINARY is fed back to the PLL at the FEEDBACK input resulting in essentially delay across the device. The PLL consists of the