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    MC100E Datasheets (500)

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    Part ECAD Model Manufacturer Description Datasheet Type PDF PDF Size Page count
    MC100E016
    		Motorola 8-BIT SYNCHRONOUS BINARY UP COUNTER Original PDF 164.33KB 8
    MC100E016
    		On Semiconductor 5V ECL 8-Bit Synchronous Binary Up Counter Original PDF 129.03KB 8
    MC100E016
    		On Semiconductor 5V ECL 8-Bit Synchronous Binary Up Counter Original PDF 918.18KB 20
    MC100E016FN
    		Motorola 8-Bit Synchronous Binary Up Counter Original PDF 164.33KB 8
    MC100E016FN
    		On Semiconductor 5V ECL 8-Bit Synchronous Binary Up Counter Original PDF 129.03KB 8
    MC100E016FN
    		On Semiconductor 5V ECL 8-Bit Synchronous Binary Up Counter Original PDF 918.18KB 20
    MC100E016FN
    		On Semiconductor 5 V ECL 8 Bit Synchronous Binary Up Counter Original PDF 92.74KB 12
    MC100E016FNG
    		On Semiconductor IC COUNTER SINGLE 8-Bit SYNC BIN UP 28PLCC RAIL Original PDF 92.73KB 12
    MC100E016FNR2
    		On Semiconductor 5V ECL 8-Bit Synchronous Binary Up Counter Original PDF 918.18KB 20
    MC100E016FNR2
    		On Semiconductor 5V ECL 8-Bit Synchronous Binary Up Counter Original PDF 129.03KB 8
    MC100E016FNR2
    		On Semiconductor 8-Bit Synch Binary Counter Original PDF 164.34KB 8
    MC100E016FNR2
    		On Semiconductor 5 V ECL 8 Bit Synchronous Binary Up Counter Original PDF 92.74KB 12
    MC100E016FNR2G
    		On Semiconductor IC COUNTER SINGLE 8-Bit SYNC BIN UP 28PLCC T/R Original PDF 92.73KB 12
    MC100E101
    		On Semiconductor 5V ECL Quad 4-Input OR/NOR Gate Original PDF 93.06KB 8
    MC100E101
    		On Semiconductor 5V ECL Quad 4-Input OR/NOR Gate Original PDF 105.15KB 8
    MC100E101
    		On Semiconductor 5V ECL Quad 4-Input OR/NOR Gate Original PDF 160.58KB 18
    MC100E101
    		On Semiconductor 5V ECL Quad 4-Input OR/NOR Gate Original PDF 918.18KB 20
    MC100E101
    		On Semiconductor 5V ECL Quad 4-Input OR/NOR Gate Original PDF 60.15KB 8
    MC100E101
    		On Semiconductor 5V ECL Quad 4-Input OR/NOR Gate Original PDF 52.2KB 10
    MC100E101
    		On Semiconductor 5V ECL Quad 4-Input OR/NOR Gate Original PDF 136.89KB 16
    ...
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    MC100E Price and Stock

    onsemi

    onsemi MC100EL04DG

    AND/NAND Gate 1-Element 2-IN 8-Pin SOIC N Tube
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    Verical () MC100EL04DG 18,228 98
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    MC100EL04DG 6,114 78
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    MC100EL04DG 4 15 Weeks 98
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    onsemi MC100EL01DG

    OR/NOR Gate 1-Element 4-IN 8-Pin SOIC N Tube
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    Verical () MC100EL01DG 4,116 98
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    MC100EL01DG 243 3
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    MC100EL01DG 2 1
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    MC100EL01DG 2 1
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    Avnet Silica MC100EL01DG 196 16 Weeks 98
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    onsemi MC100EL57DG

    Multiplexer 1-Element 4-IN 16-Pin SOIC Tube
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    Verical () MC100EL57DG 2,369 47
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    MC100EL57DG 1,815 47
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    MC100EL57DG 382 47
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    MC100EL57DG 48 47
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    MC100EL57DG 16 1
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    MC100EL57DG 11 2
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    onsemi MC100EPT23DG

    Translator, 2 Inputs, 50mA, 1.5ns, 3V to 3.6V, SOIC-8 - Rail/Tube (Alt: MC100EPT23DG)
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    Avnet Americas MC100EPT23DG Tube 678 31 Weeks 98
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    Arrow Electronics () MC100EPT23DG 38 1
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    MC100EPT23DG 7 31 Weeks 1
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    Avnet Asia MC100EPT23DG 31 Weeks 98
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    Wuhan P&S MC100EPT23DG 98 1
    • 1 $18.05
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    onsemi MC100EL15DG

    - Rail/Tube (Alt: MC100EL15DG)
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    Avnet Americas MC100EL15DG Tube 576 48
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    TME MC100EL15DG 1
    • 1 $5.19
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    Wuhan P&S MC100EL15DG 240 1
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    Find more MC100E price and stock on Findchips.com

    MC100E Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    AZ100EP16VS

    Abstract: AZ100EP16VST AZ10EP16VS AZ10EP16VST MC100EP16VS NC 1350
    Contextual Info: ARIZONA MICROTEK, INC. AZ10EP16VS AZ100EP16VS ECL/PECL Differential Receiver with Variable Output Swing FEATURES • • • • • Silicon-Germanium for High Speed Operation 150ps Typical Propagation Delay AZ100EP16VS Functionally Equivalent to ON Semiconductor MC100EP16VS


    Original     		az10ep16vsaz100ep16vs150psmc100ep16vs+5az10ep16vstaz100ep16vstaz10/100ep16vslep16vsnc 1350 PDF

    100EL91

    Abstract: MC100EL91 MC100EL91DW MC100EL91DWR2 MC100LVEL91
    Contextual Info: MC100EL91 3.3V / 5VĄTriple LVPECL / PECL Input to -5V ECL Output Translator The MC100EL91 is a triple LVPECL / PECL input to ECL output translator. The device receives standard or low voltage differential PECL signals, determined by the VCC supply level, and translates them


    Original     		mc100el91mc100lvel91r14525mc100el91/d+3100el91mc100el91dwmc100el91dwr2 PDF

    E212 transistor

    Abstract: E112 E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2 D200-400
    Contextual Info: MC10E112, MC100E112 5VĄECL Quad Driver The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock


    Original     		mc10e112mc100e112mc10e/100e112mc10e/100e111+9r14525mc10e112/de212 transistore112e212mc100e112fnmc10e112fnmc10e112fnr2d200-400 PDF

    AND8020

    Abstract: EL90 MC100EL90 MC100EL90DW MC100EL90DWR2 100EL90
    Contextual Info: MC100EL90 -3.3V / -5VĄTriple ECL Input to PECL Output Translator The MC100EL90 is a triple ECL to PECL translator. The device receives either –3.3 V or –5 V differential ECL signals, determined by the VEE supply level, and translates them to standard +5 V differential PECL


    Original     		mc100el90r14525mc100el90/dand8020+4el90mc100el90dwmc100el90dwr2100el90 PDF

    KPT25

    Abstract: EPT25 MC100EPT25 MC100EPT25D MC100EPT25DR2 MC100EPT25DT MC100EPT25DTR2 KA25 kpt25 alyw
    Contextual Info: MC100EPT25 −3.3V / −5V Differential ECL to +3.3V LVTTL Translator The MC100EPT25 is a Differential ECL to LVTTL translator. This device requires +3.3 V, -3.3 V to -5.2 V, and ground. The small outline 8-lead package and the single gate of the EPT25 make it ideal


    Original     		mc100ept25ept25r14525mc100ept25/d+7kpt25mc100ept25dmc100ept25dr2mc100ept25dtmc100ept25dtr2ka25kpt25 alyw PDF

    nippon capacitors

    Abstract: DL140 MC100E336 MC10E336
    Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3ĆBit Registered Bus Transceiver MC10E336 MC100E336 The MC10E/MC100E336 contains three bus transceivers with both transmit and receive registers. The bus outputs BUS0–BUS2 are specified for driving a 25Ω bus; the receive outputs (Q0 – Q2) are


    Original     		mc10e336mc100e336mc10e/mc100e3361500ps+41000psmc10e336/ddl140nippon capacitors PDF

    LQFP32

    Abstract: LQFP-32 MC100 MC100EPT622 MC100EPT622FA MC100EPT622FAR2
    Contextual Info: MC100EPT622 3.3V LVTTL/LVCMOS to LVPECL Translator The MC100EPT622 is a 10- Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL Positive ECL levels are used only +3.3 V and ground are required. The device has an OR- ed enable input which can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs


    Original     		mc100ept622mc100ept622lqfp-32+5r14525mc100ept622/dlqfp32mc100ept622famc100ept622far2 PDF

    marking CODE D2B

    Abstract: MC100E104 MC100E104FN MC100E104FNR2 MC10E104 MC10E104FN MC10E104FNR2 marking D3B ECL IC NAND
    Contextual Info: MC10E104, MC100E104 5VĄECL Quint 2ĆInput AND/NAND Gate The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be


    Original     		mc10e104mc100e104mc10e/100e104mc10e104fn+9eia/jesd78r14525mc10e104/dmarking code d2bmc100e104fnmc100e104fnr2mc10e104fnr2marking d3becl ic nand PDF

    MC100EP90

    Abstract: MC100EP90DT MC100EP90DTR2 MC10EP90 MC10EP90DT MC10EP90DTR2
    Contextual Info: MC10EP90, MC100EP90 -3.3V / -5VĄTriple ECL Input to LVPECL/PECL Output Translator The MC10/100EP90 is a TRIPLE ECL TO LVPECL/PECL translator. The device receives differential LVECL or ECL signals and translates them to differential LVPECL or PECL output signals.


    Original     		mc10ep90mc100ep90mc10/100ep90r14525+5mc10ep90/dmc100ep90dtmc100ep90dtr2mc10ep90dtmc10ep90dtr2 PDF

    MC100E116

    Abstract: MC100E116FN MC100E116FNR2 MC10E116 MC10E116FN MC10E116FNR2 E116
    Contextual Info: MC10E116, MC100E116 5VĄECL Quint Differential Line Receiver The MC10E/100E116 is a quint differential line receiver with emitter-follower outputs. For applications which require bandwidths greater than that of the E116, the E416 device may be of interest.


    Original     		mc10e116mc100e116mc10e/100e116r14525+6mc10e116/dmc100e116fnmc100e116fnr2mc10e116fnmc10e116fnr2e116 PDF

    8T33FS6221

    Contextual Info: DATA SHEET MC100ES6221 Freescale Semiconductor Technical Data Rev 5, 04/2005 Low Voltage 1:20 Differential ECL/PECL/HSTL Clock LowBuffer Voltage 1:20 Differential Fanout MC100ES6221 MC100ES6221 ECL/PECL/HSTL Clock Buffer PRODUCT DISCONTINUATION NOTICEFanout


    Original     		mc100es6221199707558g8t33fs6221 PDF

    KEL04

    Abstract: HL04 HEL04 e104 MC100EL04 MC10EL04 HL-04
    Contextual Info: MC10EL04, MC100EL04 5VĄECL 2ĆInput AND/NAND The MC10EL/100EL04 is a 2-input AND/NAND gate. The device is functionally equivalent to the E104 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E104, the EL04 is ideally suited for those


    Original     		mc10el04mc100el04mc10el/100el04and8003/d+7r14525mc10el04/dkel04hl04hel04e104hl-04 PDF

    KEP05

    Abstract: HEP05 MC100EP05 MC10EP05
    Contextual Info: MC10EP05, MC100EP05 3.3V / 5VĄECL 2-Input Differential AND/NAND The MC10/100EP05 is a 2–input differential AND/NAND gate. The device is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP05 is ideal for applications requiring the fastest AC performance


    Original     		mc10ep05mc100ep05mc10/100ep05lvel05+4r14525mc10ep05/dkep05hep05 PDF

    EP809

    Abstract: MC100EP809 MC100EP809FA MC100EP809FAG MC100 SY89809L MC100EP809FAR2 MC100EP809FAR2G
    Contextual Info: MC100EP809 3.3V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable http://onsemi.com Description The MC100EP809 is a low skew 1−to−9 differential clock driver, designed with clock distribution in mind, accepting two clock sources into


    Original     		mc100ep809mc100ep809/dep809mc100ep809fa+5mc100ep809fagmc100sy89809lmc100ep809far2mc100ep809far2g PDF

    MC10EP016

    Abstract: MC100EP016 MC10E016
    Contextual Info: MC10EP016, MC100EP016 3.3V / 5V ECL 8−Bit Synchronous Binary Up Counter The MC10/100EP016 is a high−speed synchronous, presettable, cascadeable 8−bit binary counter. Architecture and operation are the same as the MC10E016 in the ECLinPS family. The counter features internal feedback to TC gated by the TCLD


    Original     		mc10ep016mc100ep016mc10/100ep016mc10e016+1mc10ep016/d PDF

    EP29

    Abstract: MC100EP29 MC10EP29
    Contextual Info: MC10EP29, MC100EP29 3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset http://onsemi.com Description The MC10/100EP29 is a dual master−slave flip−flop. The device features fully differential Data and Clock inputs as well as outputs.


    Original     		mc10ep29mc100ep29mc10/100ep29mc10/100el29+2mc10ep29/dep29 PDF

    KV05

    Abstract: KVL05 MC100EL05 MC100LVEL05 MC100LVEL05MNR4G
    Contextual Info: MC100LVEL05 3.3V ECL 2-Input Differential AND/NAND Description The MC100LVEL05 is a 2-input differential AND/NAND gate. The device is functionally equivalent to the MC100EL05 device and operates from a 3.3 V supply voltage. With propagation delays and output transition times equivalent to the EL05, the LVEL05 is ideally


    Original     		mc100lvel05mc100el05lvel05mc100lvel05/d+3kv05kvl05mc100lvel05mnr4g PDF

    MC100E416

    Abstract: MC10E416 MC10E416FN
    Contextual Info: MC10E416, MC100E416 5V ECL Quint Differential Line Receiver Description The MC10E416/100E416 is a 5-bit differential line receiving device. The 2.0 GHz of bandwidth provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators.


    Original     		mc10e416mc100e416mc10e416/100e416mc10e416/d+1mc10e416fn PDF

    MC100E171

    Abstract: MC10E171 MC10E171FN
    Contextual Info: MC10E171, MC100E171 5V ECL 3-Bit 4:1 Multiplexer Description The MC10E/100E171 contains three 4:1 multiplexers with differential outputs. Separate Select controls are provided for the leading 2:1 MUX pairs see logic symbol . The three Select inputs control which one of the four data inputs in each case is propagated to


    Original     		mc10e171mc100e171mc10e/100e171mc10e171/d+1mc10e171fn PDF

    MC100E151

    Abstract: MC10E151 MC10E151FN
    Contextual Info: MC10E151, MC100E151 5V ECL 6-Bit D Register Description The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 or both go HIGH. The asynchronous


    Original     		mc10e151mc100e151mc10e/100e151mc10e151/d+1mc10e151fn PDF

    MC100E150

    Abstract: MC10E150 MC10E150FN
    Contextual Info: MC10E150, MC100E150 5V ECL 6-Bit D Latch Description The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the


    Original     		mc10e150mc100e150mc10e/100e150mc10e150/d+1mc10e150fn PDF

    LVDS100

    Abstract: MC100EP16 SN65LVDS100 SN65LVDS100D SN65LVDS100DGK SN65LVDS101 SN65LVDT100 SN65LVDT100D SN65LVDT101
    Contextual Info: SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 www.ti.com SLLS516B − AUGUST 2002 − REVISED SEPTEMBER 2003 DIFFERENTIAL TRANSLATOR/REPEATER FEATURES D Designed for Signaling Rates 1 . 2 Gbps D Total Jitter < 65 ps D Low-Power Alternative for the MC100EP16


    Original     		sn65lvds100sn65lvdt100sn65lvds101sn65lvdt101+6slls516bmc100ep16lvds100sn65lvds100dsn65lvds100dgksn65lvdt100d PDF

    100EL30

    Abstract: MC100EL30 MC100EL30DW
    Contextual Info: MC100EL30 5V ECL Triple D Flip−Flop with Set and Reset The MC100EL30 is a triple master−slave D flip−flop with differential outputs. Data enters the master latch when the clock input is LOW and transfers to the slave upon a positive transition on the


    Original     		mc100el30mc100el30/d100el30mc100el30dw PDF

    KEP16

    Abstract: LVEL16 MC100EP16 MC10EP16
    Contextual Info: MC10EP16, MC100EP16 3.3V / 5V ECL Differential Receiver/Driver Description http://onsemi.com MARKING DIAGRAMS* 8 8 1 SOIC−8 D SUFFIX CASE 751 1 8 8 1 Features TSSOP−8 DT SUFFIX CASE 948R • 220 ps Typical Propagation Delay • Maximum Frequency > 4 GHz Typical


    Original     		mc10ep16mc100ep16kep16hep16+3506aamc10ep16/dlvel16 PDF