MBITS Search Results

of TX6A RX6A

Abstract: RX6A tx2c transmitter RX6a 1211 TX1B TXC-06885 diode GFP AA tx6c TX5b rx5b Ethernet over SONET mapper
Contextual Info: Envoy -CE4 Device SPI-3 to Ethernet Controller TXC-06885 DATA SHEET PRODUCT PREVIEW • 4 Configurable Media Access Controllers MACs • Each MAC is configurable as 8 Fast Ethernet ports (10/100 Mbits/s) or 2 Fast Ethernet ports with extended buffers or 1 Gigabit Ethernet port (10/100/1000 Mbits/s)

b9236

Abstract: B9233 CY7B923-jC CY7B933 CY7B923 foto sensor B9237 7B923
Contextual Info: CY7B923 CY7B933 HOTLink Transmitter/Receiver Features • • • • • • • • • • • • • • • • • • • that transfer data over high-speed serial links fiber, coax, and twisted pair . Standard HOTLink data rates range from 160-330 Mbits/second. Higher speed HOTLink is also available for high speed applications (160-400 Mbits/second), as

Contextual Info: Advance Data Sheet September 1999 LU3X31T-T64 Single-Port 3 V 10/100 Ethernet Transceiver TX Overview The LU3X31T-T64 is a fully integrated 10/100 Mbits/s physical layer device with an integrated transceiver. It is provided in a 64-pin TQFP package with low-power operation and powerdown

MS 6701

Abstract: 6712 SFH6705 IR 30 S1
Contextual Info: SFH6700/6719 SFH6701/6711 SFH6702/6712 SFH6705 Low Input Current Logic Gate Optocoupler FEATURES • Data Rate 5.0 MBits/s 2.5 MBit/s over Temperature • Buffer • Isolation Test Voltage, 5300 VRMS for 1.0 s • TTL, LSTTL and CMOS Compatible • Internal Shield for Very High Common Mode

Contextual Info: Advance Data Sheet August 1998 LU5M31 Gigabit Ethernet Media Access Controller MAC Overview The LU5M31 is a single-port 1 Gbit/s MAC that incorporates physical coding sublayer (PCS) functionality. The LU5M31 is intended to enhance 10/ 100 Mbits/s Ethernet frame switching, multiple port

RCR20

Abstract: TLHR RCR1511 RCR20 resistor CS61535A CS61574A CS61575 CS61581 CS62180A CS62180B
Contextual Info: CS62181 — Advanced Product Databook CIRRUS LOGIC FEATURES • Integrated E1 Framer for 2.048 Mbits/s Applications ■ Meets ITU-T G.704, G.706, and G.732, ETSI ETS 300-011, and ITU-T 1.431 ■ Support for CRC-4 Framing Standards and CAS/CCS Signaling Formats

WD10C22B

Abstract: WD42C22 wd50c12 WD2010b DIODE CL04 12 mfm to nrz 3 phase pump guard controller 57vcc y1q1 C106
Contextual Info: W D10C22B Self-Adjusting Data Separator FEATURES • Designed specifically for the industry standard W D42C22/W D50C12 Hard Disk Controllers and ST506/412 type W inchester disk drives • Provides pin-selectable MFM 5 Mbits/sec or RLL (to 10 Mbits/sec) • Provides all processing of the sensitive

SN75LBC776

Abstract: SN75LBC777
Contextual Info: SN75LBC777 SINGLE CHIP GEOPORT/AppleTalk TRANSCEIVER SLLS227 – SEPTEMBER 1996 D D D D D D D D Single-Chip Interface Solution for the 9-Pin GeoPort Peripheral Data CircuitTerminating Equipment DCE for the Intelligent Network Port Designed to Operate up to 4-Mbits/s Full

3G ATM

Abstract: L-LLP1601621
Contextual Info: Product Brief LLP-W Link Layer Processor-Wireless Overview F e at u r e s n Line interfaces: — Up to 32 Mbits/s bidirectional bandwidth through channelized OC-3/STM-1: • An NSMI port 51.84 Mbits/s supports up to 16 DS1/J1 links or up to 16 E1 links.

Contextual Info: Advance Data Sheet November 1999 LU3X32FT Two-Port 3 V 10/100 Ethernet Transceiver TX/FX Overview The LU3X32FT is a fully integrated two-port 10 Mbits/s/100 Mbits/s physical layer device with transceiver. This part was designed for 10 Mbits/s/ 100 Mbits/s applications where board space, cost,

pin diagram of ic 7495 shift register

Contextual Info: Advance Data Sheet January 2000 TA16-Type 2.5 Gbits/s Translight Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer Applications • Telecommunications: — Inter- and intraoffice SONET/SDH — Subscriber loop — Metropolitan area networks

Contextual Info: Product Brief Ultramapper II 622/155 Mbits/s SDH/SONET x DS3/E3/DS1/E1/DSO Mapper Ultramapper II defines a family of highly versatile, system-on-a-chip SOC solutions which integrate SDH/SONET section, line, path, and tributary termination functions with M13/E13 multiplex functions, grooming/time slot

circuit diagram of PAM transmitter and receiver

Abstract: PAM-5 17-LEVEL 1000base high speed line driver GMII layout
Contextual Info: Preliminary - Content Subject to Change L80601 Ultra Low Power 10/100/1000 Mbits/s PHY Preliminary Datasheet The L80601 is a full-featured Physical Layer PHY transceiver with integrated Physical Media Dependent (PMD) sublayers to support 10BASE-T, 100BASE-TX, and 1000BASE-T Ethernet protocols.

Contextual Info: Standard Products UT200SpWPHY01 SpaceWire Physical Layer Transceiver Datasheet August, 2006 INTRODUCTION FEATURES ‰ 2-bit Serializer/Deserializer SerDes functionality ‰ LVDS physical layer ‰ Data rates to 200 Mbits/sec ‰ Data/Strobe transmit skew <500pS

8X300

Abstract: WD1100-06
Contextual Info: WESTERN O R P O DIGITAL R A T I O N WD1100-06 C WD1100-06 ECC/CRC Logic FEATURES • 32-BIT COMPUTER SELECTED POLYNOMIAL DATA TRANSFER RATES TO 5.25 MBITS/SEC • SINGLE BURST CORRECTION TO 8 BITS SERIAL CHECK/SYNDROME BIT PROCESSING • MULTIPLE BURST DETECTION

THGBM1G5D2EBAI7

Abstract: THGBM1G8D8EBAI2 THGBM1G6D4EBAI4 THGBM1G4D1EBAI7 TH58NVG4S0DTG20 toshiba THGBM1G4D1EBAI7 TH58NVG4 toshiba TH58NVG5 THGBM1G THGBM
Contextual Info: SEMICONDUCTOR GENERAL CATALOG Memories and Storage Devices NAND Flash Memory 1 2009-8 SCE0004I NAND Flash Memory SLC Small Block Capacity Part Number 512 Mbits TC58DVM92A3TA00 TC58DVM92A3BAJW TC58DVG02A3TA00 512 Mbits 1 Gbits Access Time Program/Erase Time typ.

TH58NVG4S0DTG20

Abstract: THGBM1G5D2EBAI7 TH58NVG5S0DTG20 THGBM1G6D4EBAI4 TC58NVG3S0DTG00 THGBM1G4D1EBAI7 THGVS4G3D1EBAI8 THGBM1G8D8EBAI2 tc58nvg3 TH58NVG4
Contextual Info: 東芝半導体製品総覧表 2009 年 7 月版 メモリ／ストレージデバイス NAND 型フラッシュメモリ 1 2009/7 SCJ0004N NAND 型フラッシュメモリ SLC 小ブロック 容量 512 Mbits 512 Mbits 1 Gbits 品 番 ページサイズ bit

E1110

Abstract: structure of GMII packet with VLAN Tag E1110 S 20 diode E1110 mac 226 E-1110 TXSV37 E110.000
Contextual Info: TECHNICAL MANUAL E-1110 10/100/1000 Mbits/s Ethernet MAC Preliminary April 2001 R14024 This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified either the functional descriptions, or the electrical and mechanical specifications using

JESD97

Abstract: NAND04G-B2D TSOP48 outline
Contextual Info: NAND16GW3B4D 16-Gbit 4 x 4 Gbits , two Chip Enable, 2112-byte page, 3 V supply, single level, multiplane, NAND flash memory Preliminary Data Features • High-density NAND flash memory – 16 Gbits of memory array – 512 Mbits of spare area – Cost-effective solutions for mass storage

JESD97

Abstract: NAND08GW3C2B NAND16GW3C4B 16Gbit
Contextual Info: NAND16GW3C4B 16-Gbit 2 x 8 Gbits , two Chip Enable, 2112-byte page, 3 V supply, multilevel, multiplane, NAND flash memory Preliminary Data Features • High density multilevel cell (MLC) flash memory – 16 Gbits of memory array – 512 Mbits of spare area

128W18

Abstract: 28f128w18t Intel SCSP 28F128W18B 28F640W18T 128W-1 128W18B micron flash otp
Contextual Info: 128-Mbit 1.8 Volt Intel Wireless Flash Memory W18 + 32-Mbit PSRAM Stacked-CSP Family Datasheet Product Features • ■ ■ ■ Flash Architecture — Flexible, Multiple-Partition, DualOperation: Read-While-Write / ReadWhile-Erase — 32 Partitions, 4 Mbits each

MR29

Abstract: DNC3X3625 MR20 MR21 MR30 MR31 "network interface cards"
Contextual Info: Advance Data Sheet March 2000 DNC3X3625 Hex 10/100 Mbits/s Ethernet Transceiver Macrocell Features Hex 100 Mbits/s FX Transceiver Hex 10 Mbits/s Transceiver • Compatible with IEEE 802.3u 100Base-FX standard. ■ DSP based. ■ ■ Compatible with IEEE * 802.3 10Base-T standard

LD4300

Abstract: gpr detector viterbi
Contextual Info: LD4300 GALAXY Advance Information FEATURES General • 150 - 850 Mbits/sec data rate operation · Extended Class 4 Partial Response with Viterbi detection EPRML system or · Generalized Class 4 Partial Response with Viterbi detection (GPRML) system · Rate 32/34 and 96/102 Trellis Constraint code with Post-Processor

hdlc

Abstract: hdlc framing cesopsn
Contextual Info: Product Brief LLP Link Layer Processor Overview F e at u r e s n Line interfaces: — Full termination of a channelized OC-3/STM-1 via three NSMI interfaces • Up to three NSMI ports 51.84 Mbits/s each supporting up to 84 DS1/J1 links or 63 E1 links. — Supports up to 16 LIU ports with