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MATRA

Contextual Info: Te m ic HM 65764 MATRA MHS 8K x 8 High Speed CMOS SRAM Description The HM 65764 is a high speed CMOS static RAM organized as 8192x8 bits. It is manufactured using MHS high performance CMOS technology. Access times as fast as 15 ns are available with maximum power consumption of only 743 mW.

Contextual Info: 4*ìE T> Sabf l MSb 000E073 174 _ I MMHS MATRA M H S January 1991 Preliminary M 65M748 HI-REL DATA SHEET 256 k x 8 SRAM MODULE FEATURES • HIGH DENSITY 2 MEGABIT SRAM MODULE ASYNCHRONOUS ■ MILITARY ACCESS TIME : 35*/45/55 ns 5 VOLT OPERATION ■ LOW POWER CONSUMPTION

parallel to serial conversion

Abstract: diode 1432
Contextual Info: Temic COMLIB MATRA MHS ATM Physical Layer ASIC Macro Library for 1.432 Description The ASIC Macro Library is consisting of specific macros which are supporting the ATM 1.432 Physical M edium Sublayer up to 622 MBit/s serial communication. This macro family, which is targeted

MG1140E

Abstract: 000GATES
Contextual Info: Tem ic Array MATRA MHS MG1RT : Radiation Tolerant 0.6|im CMOS Sea Of Gates Description TEMIC / MATRA MHS is the first European supplier for space application submicronic radiation tolerant CMOS ASICs. This is why TEMIC keeps offering a fluent way of moving up and down the quality and the space/radiation

Contextual Info: MTE » Preliminary • SñbñMSb DDG2Q61 EMG IfilMl llllr iilll MATRA ■ M H S _ T - ^ January 1991 N H S M 65M724 HI-REL DATA SHEET 128 k X 8 SRAM MODULE FEATURES . . . HIGH DENSITY 2 MEGABIT SRAM MODULE MILITARY ACCESS TIME; 35*/45/55 ns LOW POWER CONSUMPTION

Contextual Info: M^E D MATRA M H S „ Preview • 5ûbô4Sb = *^ = B ^ U 0005505 H S M=]5 ■ M M H S _ IIIÌM ÌIII January 1991 M 1 0 E 4 2 2 /M 1 0 0 E 4 2 2 DATA SHEET 256 x 4 ECL STATIC RAM FEATURES 256 X 4 BITS ORGANIZATION ULTRA HIGH SPEED/STANDARD POWER

1553 bus

Abstract: HM-65664 80C31M
Contextual Info: 5öbß45b QÜ0E3M3 1ÖT • MMHS January 1991 Preview MATRA H H S 29C530 HI-REL DATA SHEET MIL-STD-1553B PROTOCOL MANAGEMENT UNIT FEATURES . PIN PROGRAMMABLE FEATURES : - COMPATIBILITY WITH INTEL AND MOTOROLA MICROPROCESSORS - 8 OR 16 BIT INTERFACE - SUPPORT OF THREE MEMORY INTERFACE

OWTC

Contextual Info: LHE D Preview • SöböMSb OOGl'HS üöb * 1(1 HS llllrim l f l w H H S w MATRA January 1991 M H S M 6 7 1 3 3 /M 6 7 1 4 3 HI-REL DATA SHEET 2 k x 16 CMOS DUAL PORT RAM FEATURES . . . FAST ACCESS TIME MILITARY : 35 TO 55 ns VERSATILE CONTROL FOR WRITE SEPARATE

MATRA MHS

Contextual Info: Tem ic 29C84A* MATRA MHS Digital to Analog Video Decoder Description New video transmission systems like D2-MAC/packet and ISDN are being introduced today. These new services are using digital coding and decoding of video signals. The 29C84A is a digital to analog video processor

DIL 28

Abstract: soic 28
Contextual Info: MATRA M H S 4bE _ D ESI S ö b ß 4Sb QOODOn 2 OMMHS M E M O R IE S _ HIGH SPEED SRAMs PACKAGING FEATURES HM 65799 64 K x 4 Asynchronous Inputs TTL Compatible I/O E.S.D. protection > 2000 V 300 Mils Package Output Enable 73 VC C A* C 1 2 * c 3 20n

Contextual Info: LHE D MATRA M H s • SöböMSb GDÜSMEb Töl BllinHS H lftiilll January 1991 7 ^ ~ z 3 ~ / 3 DATA SHEET_ 90C1 57 1 6 , 3 8 4 x 1 6 S T A T IC R /W R A M FEATURES ■ ■ ■ ■ DATA IN AND DATA OUT LATCHES SELF-TIMED WRITE

8085 pin diagram

Contextual Info: J> SöböMSb m n ilII I W MATRA m GQGGTTS bll Novem ber 1990 M H S M8259 DATA SHEET_ PROGRAMMABLE INTERRUPT CONTROLLER FEATURES . 8085,8086,8088 COMPATIBLE . EIGHT-LEVEL PRIORITY CONTROLLER . EXPANDABLE TO 64 LEVELS . PROGRAMMABLE INTERRUPT MODES FULLY

XC3030-70PC84C

Abstract: EPM5128LC EP330PC-15 A1020 transistor A1010B-PL68C EPM5128GM EP330PC15 EP330PC XC3042-70PC84C A1020A-PL84C
Contextual Info: ULCt Cross-Reference Matra MHS Cross reference list of devices supported for ULC conversion is not exhaustiv as new devices are added regularly. Additional devices not shown in this list, may also be supported. MHS encourages you to contact your local TEMIC sales representative

Code DP

Contextual Info: Packages Flat Pack package outlines 24 pins Flat Pack 500 mils Code : D Date : 21–07–92 28 pins Flat Pack (400 mils) Code : DP MATRA MHS Date : 15–04–97 1 Packages 32 pins Flat Pack (400 mils) Code : DJ 2 Date : 04–09–96 MATRA MHS

STACK ORGANISATION

Abstract: l67201 67202
Contextual Info: L 67201/L 67202 MATRA MHS 512 x 9 & 1K × 9 / 3.3 Volts CMOS Parallel FIFO Introduction The L67201/202 implement a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow. The Expansion logic allows unlimited expansion in word

Contextual Info: HM 65788 MATRA MHS 16 K x 4 High Speed CMOS SRAM Introduction The HM 65788 is a high speed CMOS static RAM organized as 16384 × 4 bits. It is manufactured using MHS’s high performance CMOS technology. Easy memory expansion is provided by an active low chip

MATRA MHS HM* 28 pins SO pack

Contextual Info: HM 65799 MATRA MHS 64 K x 4 with OE High Speed CMOS SRAM Introduction The HM 65799 is a high speed CMOS static RAM organized as 65,536 × 4 bit. It is manufactured using MHS high performance CMOS technology. Access times as fast 20 ns are available with maximum

65756

Abstract: MHS 65756 L65756
Contextual Info: L 65756 MATRA MHS 32 K x 8 High Speed CMOS SRAM 3.3 Volt Description The L 65756 is a high speed CMOS static RAM organised as 32,768 × 8 bits. It is manufactured using MHS’s high performance CMOS technology. The L 65756 provides fast access time of 25 ns for a

i87C51

Abstract: i87C52 ST72T71N5B1 i80c51 i87c51fa sab8031 89CXX 80c154 intel PIC16C84 MICROCHIP DATA BOOK Z08614
Contextual Info: Flash MCU Order Code Guide Atmel Intel Philips AMD Microchip Zilog Matra Dallas Siemens AT89C51 i80C31 i80C51 i87C51 PCx80C31 SC80C31 PCx80C51 SC80C51 SC87C51 8751 87C51 PIC16C73 PIC16C74 Z84C01, Z84C50, Z08614 Z80C30, Z85C30, Z86C15 Z85230, Z850230, Z86C30

Contextual Info: T em ic 7508B/7509B MATRA MHS Single Rail CODEC Description 7508B p-law and 7509B (A-law) are CMOS devices containing companding CODEC and PCM voice filters on a single chip. An important feature is the operation with only a single + 5V power supply, which is useful for ISDN

Contextual Info: Tem ic 80C31/80C51 MATRA MHS CMOS 0 to 42 MHz Single-Chip 8 Bit Microcontroller Description MHS’s 80C31 and 80C51 are high performance SCMOS versions of the 8031/8051 NMOS single chip 8 bit iC. The fully static design of the MHS 80C31/80C51 allows to reduce system power consumption by bringing the

Contextual Info: Tem ic HM 65664A MATRA MHS 8 K x 8 Ultimate CMOS SRAM Description The HM 65664A is a very low power CMOS static RAM organized as 8192 x 8 bit. It is manufactured using the MHS high performance CMOS technology named super CMOS. current typical value = 0.1 nA with a fast access time at

Contextual Info: Tem ic HM 65790 MATRA MHS 16 K X 4 High Speed CMOS SRAM Separate I/O Introduction The HM 65790 is a high speed CMOS static RAM organized as 16384 x 4 bits. It is manufactured using MHS’s high performance CMOS technology. Access times as fast as 15 ns are available with maximum

Contextual Info: 41E D S ñ b ñ 4Sb GQDS107 3Ö7 • MMHS January 1991 MATRA M H S HM 65764 HI-REL DATA SHEET 8 kx 8 HIGH SPEED CMOS SRAM FEATURES . FAST ACCESS TIME : 25*/35/45/55 ns 300 AND 600 MILS WIDTH PACKAGE . LOW POWER CONSUMPTION ACTIVE : 380 mW typ STANDBY : 110 mW (typ)