MACH2 Search Results

PAL26V12

Abstract: MACH120 MACH220 PAL22V10
Contextual Info: FINAL COM’L: -10/12/15/20 IND: -14/18/24 MACH220-10/12/15/20 Lattice Semiconductor High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 68 Pins 48 Outputs 96 Macrocells 96 Flip-flops; 4 clock choices 10 ns tPD 8 “PAL26V12” blocks with buried macrocells

pal26v12

Contextual Info: CO ND ENSED COM’L : -7/1OM2/15/20 IND: -10/-12/14/18/24 MACH221 Family AdVMtaro High-Density EE CMOS Programmable Logic Devices DISTINCTIVE CHARACTERISTICS • ■ 96 Macrocells ■ 7.5 ns tpD ■ 133 M HzfcNT ■ ■ ■ 68 Pins Peripheral Component Interconnect PCI

Contextual Info: P R E L IM IN A R Y COM’L :-12/15/20 a MACH215-12/15/20 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 44 Pins 67 MHz fMAx Commercial ■ 32 Output Macrocells 38 Inputs with pull-up resistors ■ 32 Input Macrocells

A3-12

Abstract: MACH210A
Contextual Info: module dram title ' PLX TECHNOLOGY * PROPRIETARY INFORMATION * DRAM: DRAM Control MACH Engineer: DLR Product: PCI 9060/DRAM Demo Board Part Number: xxx-xxxx-xxxx Revision 1.0 08-31-95 Copyright PLX Technology, 1995 ' "device declaration dram device 'MACH210A';

C1675

Abstract: PAL22RA8
Contextual Info: CONDENSED COM’L: -12/15/20 IND: -14/18/24 MACH215-12/15/20 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 44 Pins 38 Inputs with pull-up resistors ■ 32 Output Macrocells 32 Outputs ■ 32 Input Macrocells

Contextual Info: t ’Si3 PEE FINAL COM’L :-12/15/20 a Advanced Micro Devices MACH215-12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 44 Pins 67 MHz fMAx Commercial ■ 32 Output Macrocells 38 Inputs with pull-up resistors ■ 32 Input Macrocells

Contextual Info: CO M ’L : -15/20 M IL :-20 MACH230-15/20 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 84 Pins 70 Inputs ■ 128 M acrocells 64 Outputs ■ 15 n stpD Com m ercial 128 Flip-flops; 4 clock choices 20 ns tPD M ilitary

PAL22V16

Abstract: MACH110 MACH210 MACH215 PAL22V10 MACH210-20JC MACH21S
Contextual Info: COM’L: -7/10/12/15/20, Q-12/15/20 IND: -12/14/18/24 MACH21OA-7/10/12 MACH210-12/15/20 MACH210AQ-12/15/20 High-Density EE CMOS Programmable Logic a Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 44 Pins ■ 64 Macrocells ■ 7.5 ns tpD Commercial

MACHpro

Abstract: tico 732 MACH230 PAL22V10 MACH231SP20
Contextual Info: FINAL COM’L: -10/12/15/20 IND: -12/14/18/24 MACH231SP-10/12/15/20 High-Density EE CMOS In-System Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • ■ ■ ■ JTAG-Compatible, 5-V in-system programming 100 Pins 128 Macrocells 10-ns tPD Commercial

BP1148

Abstract: mach 1 family amd MACH120 MACH220 PAL22V10 PAL26V12
Contextual Info: FINAL COM’L: -7/10/12/15/20 IND: -10/-12/14/18/24 MACH221 Family High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 68 Pins 96 Macrocells 7.5 ns tPD 133 MHz fCNT 56 Bus-Friendly Inputs and I/Os Programmable power-down mode Peripheral Component Interconnect PCI

L1144

Abstract: l0728 l0312 L0936 l0832 L1248 l2904 L4516 L7940 L0624
Contextual Info: ˆABEL 5.02 Data I/O Corp. JEDEC file for: MACH220A V1.3 Created on: Tue Oct 24 14:16:42 1995 PLX TECHNOLOGY PROPRIETARY INFORMATION BUSCTL: Local Bus Control MACH Engineer: DLR Product: PCI MPEG Board Part Number: xxx-xxxx-xxxx Revision 3.0 10-20-95 Copyright PLX Technology, 1995

MACH110

Abstract: MACH210 MACH215 PAL20RA10
Contextual Info: FINAL COM’L: -12/15/20 IND: -14/18/24 Lattice Semiconductor MACH215-12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 44 Pins ■ 38 Inputs with pull-up resistors ■ 32 Output Macrocells ■ 32 Outputs ■ 32 Input Macrocells

PAL26V12

Abstract: mach schematic turpro-1 teradyne lasar MACH120 MACH220 PAL22V10
Contextual Info: FINAL COM’L: -10/12/15/20 IND: -14/18/24 Advanced Micro Devices MACH220-10/12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 68 Pins 48 Outputs 96 Macrocells 96 Flip-flops; 4 clock choices 10 ns tPD 8 “PAL26V12” blocks with buried macrocells

Contextual Info: Preliminary COM’ L: -15/20 MIL: -20/25 a Advanced Micro Devices MACH210-15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 44 Pins 38 Inputs ■ 64 Macrocells 32 Outputs ■ 15 ns tpD Commercial 20 ns tpD Military 64 Flip-flops

Contextual Info: F IN A L COM’L: -12/15/20 IND: -14/18/24 MACH215-12/15/20 High-Density EE CMOS Programmable Logic a Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 44 Pins ■ 32 Output Macrocells ■ ■ ■ ■ 67 MHz fMAx external Commercial 42 MHz fMAx external Industrial

Contextual Info: FINAL COM’L: -12 a MACH210AQ-12 Advanced Micro Devices High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 44 Pins ■ 32 Outputs ■ 64 Macrocells ■ 64 Flip-flops; 2 clock choices ■ 12 ns tPD Commercial ■ 4 “PAL22V16” blocks with buried macrocells

PAL26V12

Abstract: PAL 007 PAL 007 A MACH120 MACH220 PAL22V10
Contextual Info: FINAL COM’L: -10/12/15/20 IND: -14/18/24 MACH220-10/12/15/20 Lattice/Vantis High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 68 Pins 48 Outputs 96 Macrocells 96 Flip-flops; 4 clock choices 10 ns tPD 8 “PAL26V12” blocks with buried macrocells

HP3070

Abstract: PALCE22V10 PALCE26V12
Contextual Info: MACH 1 & 2 FAMILIES 1 FINAL COM’L: -7/10/12/15 IND: -10/-12/14/18 MACH 1 & 2 Families MACH221SP-7/10/12/15 High-Performance EE CMOS In-System Programmable Logic DISTINCTIVE CHARACTERISTICS ◆ JTAG-Compatible, 5-V In-system programming ◆ 100 Pins in PQFP and TQFP

pal 007a

Abstract: MACH21D PAL 006A PAL 002a pal 005a MACH110 MACH210 MACH215 PAL22V10 PAL22V16
Contextual Info: FINAL COM’L: -7/10/12/15/20, Q-12/15/20 IND: -12/14/18/24 M ACH21OA-7/10/12 MACH210-12/15/20 MACH210AQ-12/15/20 a Advanced Micro Devices High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • Peripheral Component Interconnect PCI compliant

teradyne

Abstract: teradyne lasar MACH130 MACH230 PAL22V10
Contextual Info: FINAL MACH231-6 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 84 Pins Programmable power-down mode 128 Macrocells 64 Outputs 6 ns tPD 128 Flip-flops; 4 clock choices 166 MHz fCNT 8 “PAL32V16” blocks with buried macrocells 70 Bus-Friendly Inputs

tms 3755

Abstract: teradyne flex tester PAL26V12 PALCE22V10 MACH220 teradyne lasar PALCE* programming
Contextual Info: PRELIMINARY COM’L: -7/10/12/15 IND: -10/-12/14/18 MACH221SP Family High-Density EE CMOS In-System Programmable Logic V A N T I S The Programmable Logic Company From AMD DISTINCTIVE CHARACTERISTICS • JTAG-Compatible, 5-V In-system programming ■ Programmable power-down mode

MACH110

Abstract: PA-MACH210-Q06T FPQ-44 PH209 MACH210 mach 1 to 5 from amd enplas socket
Contextual Info: PA-MACH210-Q06T Data Sheet 44 pin QFP socket/28 pin DIP 0.6” plug Supported Device/Footprints Adapter Construction Using this adapter, the AMD MACH110, 210 & 215 in the QFP package can be programmed on DIP programmers. The adapter is made up of 3 sub-assemblies. They assemble via

PAL32V16

Abstract: AMD MACH435
Contextual Info: CO ND ENSED COM’L: -6/7.5/10/12/15/20 MACH231-6/7/10/12/15/20 & need AdvaM "££ i/licro High-Density EE CMOS Programmable Logic Devices DISTINCTIVE CHARACTERISTICS • 84 Pins ■ Programmable power-down mode ■ 128 Macrocells ■ 64 Outputs ■ 6 tpD

Contextual Info: COM’L: -15/20 a MACH230-15/20 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 84 Pins ■ 64 Outputs ■ 128 Macrocells ■ 128 Flip-flops; 4 clock choices ■ 15nstPD ■ 8 “PAL26V16” blocks with burled macrocells