M74LS2 Search Results

BCD-TO-7-SEGMENT DECODER

Abstract: m74ls248p M74LS247P M74LS48P m74ls48 M74LS47P
Contextual Info: MITSUBISHI LSTTLs M74LS248P B C D -TO -7 -SEGM ENT D EC O D ER /D R IVER A C TIV E -H IG H O U TP U T DESCRIPTION The M 7 4L S 24 8P is a semiconductor integrated circuit pro­ vided w ith a BCD-to-7-segment decoder/driver function and 2kohm (typ ) pull-up resistor outputs.

M74LS247P

Abstract: 7 segment 4" LT display M74LS47P 4 digits 7-segment led display display 7 segment smd 4 digits 7-segment display cl BCD-TO-7-SEGMENT DECODER 4 digits 7-segment led display cl BCD-TO-7-SEGMENT 7 segment 4 LT display
Contextual Info: MITSUBISHI LSTTLs M74LS247P B C D -TO -7-S EG M E N T D E C O D E R /D R IV E R A C T IV E -L O W O U TP U T DESCRIPTION The M74LS247P is a semiconductor integrated circuit PIN CONFIGURATION (TOP VIEW) provided with BCD-to-7-segment decoder/driver function

20-PIN

Abstract: M74LS298P M74LS298
Contextual Info: MITSUBISHI LS TT Ls M 74LS298P QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE DESCRIPTION The M74LS298P is a sem iconductor integrated circuit PIN CONFIGURATION TOP VIEW which containing fo u r 2-line to 1-line m ultiplexers provided w ith a tem porary storage circu it w ith common selection

mitsubishi cab

Abstract: M74LS241P M74LS243P 20-PIN
Contextual Info: MITSUBISHI LSTTLs M74LS243P QUADRUPLE BUS TRANSCEIVER WITH 3-STATE OUTPUT NONINVERTED DESCRIPTION The M 74L S 24 3P PIN CONFIGURATION (TOP VIEW) is a semiconductor integrated circuit containing 4 bus transmitters/receivers w ith 3-state non­ inverted outputs.

M74LS27P

Contextual Info: MITSUBISHI LSTTLs M74LS27P TRIPLE 3-INPUT POSITIVE NOR GATE DESCRIPTION The M74LS27P is a semiconductor PIN CONFIGURATION TOP VIEW integrated circu it containing three trip le -in p u t positive NOR and negative NAN D gates. “ W FEATURES IB • High breakdown in p u t voltage (V| ^ 15V)

74LS20P

Contextual Info: MITSUBISHI LSTTLs M74LS20P DUAL 4 -IN P U T P O S IT IV E NAND GATE DESCRIPTION The M 74LS 20P is a semiconductor integrated containing tw o 4-input positive N A N D circuit gates, usable as negative-logic N O R gates. FEATURES • High breakdown input voltage V | > 15V

74LS04P

Abstract: 2294a
Contextual Info: MITSUBISHI LSTTLs M74LS257AP QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER W ITH 3-STATE OUTPUT DESCRIPTION The M 7 4L S 25 7A P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing fo ur 2-line to 1-line data selector/m ultiplexer

74LS24P

Contextual Info: MITSUBISHI LSTTLs M74LS24P QUADRUPLE 2-IN P U T POSITIVE NAND SCHMITT TRIGGER D E S C R IP T IO N T h e M 7 4 L S 2 4 P is a s e m ico n d u c to r in teg rated c irc u it c o n ­ ta in in g fo u r 2 -in p u t po sitive-logic N A N D gates having a s c h m itt trigg er fu n c tio n and negative-logic N O R gates.

74LS22P

Contextual Info: MITSUBISHI LSTTLs M74LS22P DUAL 4 -IN P U T P O S IT IV E NAND GATE W IT H OPEN COLLECTOR OUTPUT DESCRIPTION The M 74LS22P c o n ta in in g tw o PIN CONFIGURATION TOP VIEW is a s em ico n d u c to r 4 -in p u t po sitive-logic in teg rated NAND c irc u it

74LS48p

Abstract: M74LS247P BCD-TO-7-SEGMENT
Contextual Info: MITSUBISHI LSTTLs M74LS248P B C D -TO -7 -SEGM ENT D EC O D ER /D R IVER A C TIV E -H IG H O U TP U T DESCRIPTION The M 7 4L S 24 8P is a semiconductor integrated circuit pro­ vided w ith a BCD-to-7-segment decoder/driver fu nction and 2kohm (typ ) pull-up resistor outputs.

M74LS221P

Abstract: Dual Monostable Multivibrator 20-PIN
Contextual Info: MITSUBISHI LSTTLs M 7 4 L S 2 2 1 P DUAL MONOSTABLE MULTIVIBRATOR DESCRIPTION PIN CONFIGURATION TOP VIEW The M74LS221P is a semiconductor integrated circuit containing two monostable multivibrator circuits with direct reset inputs. • Pulse width excellent temperature characteristics and

M74LS244P

Abstract: 20-PIN M74LS241P
Contextual Info: M IT S U B IS H I LSTTLs M74LS244P OCTAL BUFFER/LINE DRIVERS W ITH 3-STATE OUTPUTS NONINVERTED DESCRIPTION The M 74LS244P PIN CONFIGURATION (TOP VIEW) is a s e m ico n d u c to r c o n ta in in g 2 blocks o f b u ffe rs w ith o u tp u t and com m on in teg ra te d

la 7610

Abstract: M74LS241P
Contextual Info: MITSUBISHI LSTTLs M74LS241P OCTAL BUFFER/LINE DRIVER W ITH 3-STATE OUTPUT NONINVERTED DESCRIPTION The M 7 4L S 24 1P is a semiconductor integrated circuit containing 2 buffer blocks w ith 3-state non-inverted ou t­ puts and is provided w ith ou tp u t control inputs which are

M74LS21P

Abstract: 20-PIN
Contextual Info: MITSUBISHI LSTTLs M74LS21P DUAL 4 -IN P U T P O S IT IV E AND GATE DESCRIPTION The M 74LS21P c o n ta in in g tw o is a s e m ico n d u c to r 4 -in p u t positive AND in teg rated and c irc u it negative O R gates. FEATURES • H igh b re a k d o w n in p u t voltage V | > 1 5 V

M74LS241P

Abstract: M74LS244P 20-PIN
Contextual Info: M IT S U B IS H I LSTTLs M74LS244P OCTAL BUFFER/LINE DRIVERS W ITH 3-STATE OUTPUTS NONINVERTED DESCRIPTION The M 74LS244P PIN CONFIGURATION (TOP VIEW) is a s e m ico n d u c to r c o n ta in in g 2 blocks o f b u ffe rs w ith o u tp u t and com m on in teg ra te d

74LS240P

Abstract: M74LS240P
Contextual Info: MITSUBISHI LSTTLs M 74LS240P OCTAL BUFFER/LINE DRIVERS W ITH 3-STATE OUTPUTS INVERTED DESCRIPTION The M74LS240P PIN CONFIGURATION (TOP VIEW) is a semiconductor integrated circuit containing 2 blocks of buffers with 3-state inverted output and common output control input for all 4 discrete circuits.

rs latch

Abstract: M74LS279P
Contextual Info: DESCRIPTION PIN CONFIGURATION TOP VIEW The M74LS279P is a semiconductor integrated circuit containing 4 R-S flip-flop circuits. FEATURES 1R • High breakdown input voltage (V| • • • High breakdown output voltage (Vo ^ 7V) Low power dissipation (Pd = 19mW typical)

M74LS290P

Abstract: M74LS90P 20-PIN decade counter
Contextual Info: M ITSU BISH I LSTTLs M74LS290P DECADE COUNTER DESCRIPTION The M 74L S 29 0P PIN CONFIGURATION TOP VIEW is a semiconductor integrated cirucit containing an asynchronous decade counter function w ith direct reset and direct 9-set inputs. D IR E C T 9 S ET S q ( 9 ) i

T flip flop IC

Abstract: M74LS273P T flip flop pin configuration 20-PIN M74LS273 MITSUBISHI C
Contextual Info: MITSUBISHI LSTTLs M74LS273P OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP FLOP WITH RESET DESCRIPTION The M 7 4L S 27 3P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing 8 D -type positive edge-triggered flip -flo p circuits DIRECT RESET

S295B

Contextual Info: MITSUBISHI LSTTLs M74LS295BP 4 -B IT S H IFT REGISTER W IT H 3-S TA TE O U TPU T DESCRIPTION PIN CONFIGURATION TOP VIEW The M74LS295BP is a semiconductor integrated circuit containing a 3-state output 4-bit serial/parallel input serial/ parallel output shift register function.

4 bit even and odd parity checker

Abstract: 20-PIN M74LS280P 4 bit even parity generator circuit
Contextual Info: MITSUBISHI LSTTLs M74LS280P 9 -B IT ODD/EVEN PARITY GENERATOR/CHECKER DESCRIPTION The M 74LS 280P is a semiconductor integrated circuit containing a 9-b it parity generator/checker function. FEATURES • Easy expansion of bits w ith cascade connection •

74LS27P

Abstract: M74LS27P 20-PIN
Contextual Info: M ITSUBISHI LSTTLs M 74 LS2 7P TR IP LE 3 -IN P U T P O S IT IV E NOR GATE DESCRIPTION The M74LS27P is a semiconductor PIN CONFIGURATION TOP VIEW integrated circu it containing three trip le -in p u t positive NOR and negative NAN D gates. “ W FEATURES

M74LS157P

Abstract: M74LS257AP 251C M74LS257
Contextual Info: MITSUBISHI LS TTLs M74LS257AP QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER W ITH 3-STATE OUTPUT DESCRIPTION PIN CONFIGURATION TOP VIEW The M 7 4L S 25 7A P is a semiconductor integrated circuit containing fo ur 2-line to 1-line data selector/m ultiplexer

Contextual Info: MITSUBISHI LSTTLs M74LS243P QUADRUPLE BUS TRANSCEIVER W ITH 3-STATE OUTPUT NONINVERTED DESCRIPTION The M 74L S 24 3P PIN CONFIGURATION (TOP VIEW) is a semiconductor integrated circuit containing 4 bus transmitters/receivers w ith 3-state non­ inverted outputs.