M13S Search Results

Contextual Info: ESMT M13S128168A Operation temperature condition -40°C~85°C Revision History Revision 1.0 03 Jan. 2007 - Original Revision 1.1 (19 Mar. 2008) - Add BGA package - Modify the waveform of Power up & Initialization Sequence - Modify the θ value of TSOPII package dimension

Contextual Info: ESMT M13S2561616A Revision History Revision 0.1 28 Apr. 2006 - Original Revision 1.0 (07 Jun. 2006) - Delete Preliminary at ever page - Revise typing error of page1 Revision 1.1 (09 May. 2007) - Modify PD, DC specifications and MRS Revision 1.2 (12 Jun. 2007)

Contextual Info: ESMT M13S64164A Revision History Revision 0.1 23 Oct. 2006 - Original Revision 0.2 (06 Jun. 2007) - Add BGA type spec Revision 0.3 (20 Jul. 2007) - Modify BGA assignment Revision 0.4 (01 Oct. 2007) - Modify IDD spec. Revision 1.0 (20 Nov. 2007) - Delete “Preliminary”

M13S32321A

Contextual Info: ESMT M13S32321A DDR SDRAM 256K x 32 Bit x 4 Banks Double Data Rate SDRAM Features z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe DQS z On-chip DLL z Differential clock inputs (CLK and CLK )

M13S128324A-5BG

Abstract: M13S128324A
Contextual Info: ESMT M13S128324A DDR SDRAM 1M x 32 Bit x 4 Banks Double Data Rate SDRAM Features z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe DQS z On-chip DLL z Differential clock inputs (CLK and CLK )

Contextual Info: ESM T M13S2561616A 2K DDR SDRAM 4M x 16 Bit x 4 Banks Double Data Rate SDRAM Features Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe (DQS) Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition

Contextual Info: ESM T M13S128324A 2M DDR SDRAM 1M x 32 Bit x 4 Banks Double Data Rate SDRAM Features Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe (DQS) Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition

Contextual Info: ESM T M13S64164A 2Y DDR SDRAM 1M x 16 Bit x 4 Banks Double Data Rate SDRAM Features Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe (DQS) Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition

Contextual Info: ESM T M13S2561616A 2A Automotive Grade DDR SDRAM 4M x 16 Bit x 4 Banks Double Data Rate SDRAM Features Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe (DQS) Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition

Contextual Info: ESM T M13S128168A 2N Operation Temperature Condition -40°C~85°C DDR SDRAM 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Features Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe (DQS) Differential clock inputs (CLK and CLK )

cke02

Abstract: 100L
Contextual Info: ESMT M13S64322A Preliminary Revision History Revision 0.5 May 03, 2007 - Delete BGA ball name of packing dimensions Revision 0.4 (May 14,2002) - Change AC Parameters Revision Rev. 0.3 Rev. 0.4 Version -4 -5 -4 -5 tRC 13 tCK 11 tCK 14 tCK 12 tCK tRP 4 tCK

esmt m13s2561616a

Abstract: M13S2561616A -5T M13S2561616A
Contextual Info: ESMT M13S2561616A Operation Temperature Condition -40~85°C Revision History Revision1.0 19 Oct. 2007 - Original Revision1.1 (06 Dec. 2007) - Add BGA package Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2007 Revision : 1.1 1/49 ESMT

M13S128324A

Contextual Info: ESMT M13S128324A Operation Temperature Condition -40~85°C Revision History Revision 1.0 Dec. 14 2007 -Original Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2007 Revision : 1.0 1/49 ESMT M13S128324A Operation Temperature Condition -40~85°C

CKE 2009

Abstract: M13S64164A CL301
Contextual Info: ESMT M13S64164A Operation Temperature Condition -40°C~85°C DDR SDRAM 1M x 16 Bit x 4 Banks Double Data Rate SDRAM Features z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe DQS

Contextual Info: ESMT M13S128168A Revision History Revision 0.1 15 Jan. 2002 - Original Revision 0.2 (19 Nov. 2002) -changed ordering information & DC/AC characteristics Revision 0.1 Revision 0.2 M13S128168A - 5T M13S128168A - 6T M13S128168A - 6T M13S128168A - 7.5AB Revision 0.3 (8 Aug. 2003)

Contextual Info: ESMT Prelinminary M13S2561616A Revision History Revision 0.1 28 Apr. 2006 - Original Elite Semiconductor Memory Technology Inc. Publication Date : Apr. 2006 Revision : 0.1 1/48 ESMT Prelinminary DDR SDRAM M13S2561616A 2M x 16 Bit x 4 Banks Double Data Rate SDRAM

M13S2561616A -5T

Abstract: M13S2561616A esmt m13s2561616a
Contextual Info: ESMT M13S2561616A Revision History Revision 0.1 28 Apr. 2006 - Original Revision 1.0 (07 Jun. 2006) - Delete Preliminary at ever page - Revise typing error of page1 Revision 1.1 (09 May. 2007) - Modify PD, DC specifications and MRS Revision 1.2 (12 Jun. 2007)

Contextual Info: ESMT M13S128168A Operation temperature condition -40°C~85°C Revision History Revision 1.0 03 Jan. 2007 - Original Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2007 Revision : 1.0 1/48 ESMT M13S128168A Operation temperature condition -40°C~85°C

Contextual Info: ESMT M13S64164A DDR SDRAM 1M x 16 Bit x 4 Banks Double Data Rate SDRAM Features z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe DQS z On-chip DLL z Differential clock inputs (CLK and CLK )

M13S256328A

Contextual Info: ESMT M13S256328A DDR SDRAM 2M x 32 Bit x 4 Banks Double Data Rate SDRAM Features z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe DQS z On-chip DLL z Differential clock inputs (CLK and CLK )

M13S64164A

Contextual Info: ESMT Preliminary M13S64164A Revision History Revision 0.1 23 Oct. 2006 - Original Revision 0.2 (06 Jun. 2007) - Add BGA type spec Revision 0.3 (20 Jul. 2007) - Modify BGA assignment Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007

Contextual Info: ESMT Preliminary M13S128168A Revision History Revision 0.1 15 Jan. 2002 - Original Revision 0.2 (19 Nov. 2002) -changed ordering information & DC/AC characteristics Revision 0.1 Revision 0.2 M13S128168A - 5T M13S128168A - 6T M13S128168A - 6T M13S128168A - 7.5AB

Contextual Info: ESM T M13S128324A 2M Operation Temperature Condition -40°C~85°C DDR SDRAM 1M x 32 Bit x 4 Banks Double Data Rate SDRAM Features Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe (DQS) Differential clock inputs (CLK and CLK )

Contextual Info: ESM T M13S128168A 2N Automotive Grade DDR SDRAM 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Features  Double-data-rate architecture, two data transfers per clock cycle  Bi-directional data strobe (DQS)  Differential clock inputs (CLK and CLK )