M-TRON MH Search Results

Contextual Info: MVE 155.520 MHz VCXO Oscillator for SONET /SDH /ATM Applications The M-tron MVE18V2BD oscillator is well suited to telecommunications applications requiring tight stability, wide deviation, low jitter and excellent linearity. The MVE18V2BD is available in the standard 14-pin DIP

Contextual Info: CZM Series Voltage Controlled Oscillator - VCO OBSOLETE OBSOLETE * 3.3V, 5V & 12V Options Available - Please Contact M-tron. 1 Any 60-200 MHz increment of pull within the limits of 0 to +5 VC 2 Any 100-300 MHz increment of pull within the limits of 0 to +5 VC

M4001

Abstract: M4002
Contextual Info: M4001/M4002 Series 2.488 GHz Surface Mount VCSO • Low Jitter - <1 ps from 12 kHz to 20 MHz • Ideal for clock smoothing application for OC-48 and OC-192 Pin Connections 1. Consult factory for extended temperature operation. 10 M-tron M4001 and M4002 Series 2488 MHz VCSO

XO-54BE

Abstract: ECS-3X8 crystal SM-49 ECS HC49S nct 040 XO-52BE VF140T p l e sq3300 Cross Reference mto13fad
Contextual Info: Cross Reference Vishay Dale CROSS REFERENCE - CRYSTALS AND OSCILLATORS VISHAY P/N ABRACON AVX KYOCERA CTS ECS ECLIPTEK EPSON FOX M-TRON PLETRONICS RALTRON RXD SARONIX VALPEY XT26T AB26T KF-26G-12P0200 — ECS-2X6 EC26T C-002RX 12.5 NC26 MMCC-2 WX26 R26 WC-26E

Contextual Info: CZM Series OBSOLETE OBSOLETE Voltage Controlled Oscillator - VCO OBSOLETE * 3.3V, 5V & 12V Options Available - Please Contact M-tron. 1 Any 60-200 MHz increment of pull within the limits of 0 to +5 VC 2 Any 100-300 MHz increment of pull within the limits of 0 to +5 VC

Contextual Info: FUJITSU M I C RO EL EC TRON IC S 23E D 374T7b2 DQQ7hSb 3 T ^ k -2 S -0 S FU JITSU CMOSV262,144jBll STATICS RANDOM 900202024801010101010000000202010201 a c c e s s ím e m o r May 1988 Edition 1.0 262,144 WORDS X 1 BIT HIGH SPEED CMOS STATIC RANDOM ACCESS MEMORY

case to106

Abstract: 2n5163 TO-106 5458 MEF3069 MEF103 2N4303 2N3070 245C 2N 5163
Contextual Info: fl-Channel Junction F E T General Purpo/e Tron/i/lor/ r BVg ss Yfs •d s s T Y P E NO. m in . m in ./m a x . m in ./m a x . V GS o ff m a x. ^iss Crss NF @ 1KHz ' gss m ax. m a x. m ax. m a x. 2.5dB 2 .5dB 4 .0 d B 4 .0 d B 1.0dB 1.0dB TYPE. 0 .1 0 n A

18-Stage Binary Counter

Abstract: block digram 22PF MN6270 A18T
Contextual Info: PANASONIC INDL/ELEK -CIO 7S D e | ^ 3 5 6 5 5 □DDb75a M •«‘Sy ,6 9 3 2 8 5 2 PANA SONIC INDl.t g.LEC TRON ICL *SV«•? ‘r SZsIiiiZZZE^ZEZ&iii MN6270 M N 6270 9 -f A ^ — X fflC M O S /C M O S Circuit for Tim e-Base Generators ^ B E S S /P in MN6270 •>

Contextual Info: For Audio Equipment MN6650A Signal Processing LSI for CD Players Overview Pin Assignment M Di ain sc te on na tin nc ue e/ d RST TLOCK FLOCK SENSE MLD MCLK MDATA TRON CLVS VSS TEST The MN6650A is a digital servo LSI for creating highprecision servo systems with completely self-adjusting

TO220B

Abstract: TO-220B 45V PNP 2A & 1.5A MH8501 2N3055 2N 6292 TO2208 MH8222 3055 3,5A METRIX+MX+220B
Contextual Info: Power Tron/i/tor/ T0-220B T O -3 r M a x im u m R a tin g s E le c tric a l C h a ra c te r is tic s @ T c - 2 5 ° C T Y P E NO. NPN PN P PD lC BVc b O LVc e o LVc e R LV Ce v b v ebo •CEX h F E @ V CE @ lc m in . /m a x . @ T c = 2 5 °C V C E s a t @ t c / ' B

Contextual Info: HE Enhanced Memory Systems Inc. 64Mbit - High Speed SDRAM 150 MHz 8Mx8, 4Mx16 HSDRAM Preliminary Data Sheet Features Description • • • The Enhanced Memory Systems SM3603 and SM3604 HighSpeed SDRAM (HSDRAM) devices are high performance versions of the proposed JEDEC PC-133 SDRAM. While

Contextual Info: 1.0 1.1 1.2 1.3 1.4 1.5 2.0 2.1 2.2 2.3 3.0. 3.1 3.2 PERFORMANCE FREQUENCY RANGE: D C -3 0 0 MHz VOLTAGE RATING: 500V RMS sea level NOMINAL IMPEDANCE: NON-CONSTANT DWV: 1500 V RMS § 60 Hz (sea level) TEMPERATURE RANGE: - 5 5 ’C TO + 8 5 ’C MATERIALS

MN103E0600YD

Abstract: SD21 SD27 SD31
Contextual Info: MN103E0600YD Type MN103E0600YD Instruction Cache 16 K-byte 4-way, set-associative Data Cashe 16 K-byte (4-way, set-associative) Package MLGA239-C-1111 7.5 ns (at 1.8 V tolerance = ±5% , 133 MHz) Minimum Instruction Execution Time Interrupts • XIRQ x 8 • NMI • Timer × 14 • DMAC × 4 • WDT • SIO × 6 • I2C × 2 • Asynchronous bus error

Contextual Info: W F1M 32B-XXX3 W h it e E l e c t r o n ic D e s ig n s C o r p o r a t i o n 1Mx32 3.3V FLASH MODULE FEATURES • Access Tim es of 100,120, 150ns ■ Boot Code Sector Architecture Bottom ■ Packaging ■ Low Power CMOS, 1,0mA Standby • 66 pin, PGA Type, 1.185" square, Hermetic Ceramic

Contextual Info: WME128K8-XXX W hite El e c t r o n ic D esigns C o r p o r a t i o n 128Kx8 CMOS MONOLITHIC EEPROM. SMD 5962-96796 FEATURES FIG. 1 • Read Access Tim es of 1 2 0 ,1 4 0 ,1 5 0 , 200, 250, 300ns PIN CONFIGURATION ■ JEDEC Approved Packages 32 DIP 32 CSOJ

Contextual Info: WME128K8-XXXE W hite El e c t r o n ic D esigns C o r p o r a t i o n 128Kx8 CMOS MONOLITHIC EEPROM ADVANCED* FEATURES FIG. 1 • Access Tim es of 150, 200, 250, 300ns PIN C O N FIG U R A TIO N ■ JEDEC Approved Packages 3 2 D IP • 32 pin, Hermetic Ceramic, 0.600" DIP Package 300

Contextual Info: J5SEnhanced Memory ^sterns Inc. 64Mbit - High Speed SDRAM 8Mx8, 4Mx16 HSDRAM Preliminary Data Sheet Features Description • • • The Enhanced Memory Systems SM3603 and SM3604 HighSpeed SDRAM HSDRAM devices are high performance versions of the proposed JEDEC PC-133 SDRAM. While

Contextual Info: Memory Systems Inc. y ^ Industrial Temperature 16Mbit Enhanced Synchronous DRAM 1 Mx16 ESDRAM Preliminary Data Sheet Features Description • • As a JEDEC superset standard, the Enhanced Synchronous DRAM ESDRAM is an evolutionary modification to the JEDEC standard SDRAM. The industrial temperature grade

ESDRAM

Abstract: Enhanced SDRAM
Contextual Info: JÇBEnhanced Memory Systems Inc. 168-pin Enhanced SDRAM DIMM 8MB, 16MB, 32MB DIMM Preliminary Data Sheet Pin Assignments Features • • • • • • • • • • • JEDEC Standard 168-pin SDRAM DIMM PC-100 Spec Compliant - Lowest Latency Single 3.3V + 0.3V Power Supply

Contextual Info: Memory Systems Inc. 3 !nd^ st^ TenJPo i S am 64Mbit - High Speed SDRAM 8Mx8, 4Mx16 HSDRAM Preliminary Data Sheet Features Description • • • • The Enhanced Memory Systems SM3603 and SM3604 HighSpeed SDRAM HSDRAM devices are high performance versions of the proposed JEDEC PC-133 SDRAM. The

Contextual Info: Enhanced Memory Systems Inc. PC-133 HSDRAM 256MB, 512MB DIMM Preliminary Data Sheet Features • • • • • • • • • • JEDEC Standard PC-133 SDRAM DIMM Highest Density PC-133 SDRAM Unbuffered DIMMs 256 Mbit HSDRAM Chip Components Fast 4.6 ns Clock Access Time

Contextual Info: i^ Ä S ? is > in c . 4 M x 4 , 2 M x 8 , 1 M x 1 6 preliminary Data sheet 1 6 M b it E n h a n c e d S y n c h ro n o u s D R A M Overview Features • High Perform ance: CAS latency = 2 fcK Clock Frequency tcK2 Clock Cycle *AC2 Clock Access Tim e • P rogram m able Burst Length: 1,2,4,8,full-page

Contextual Info: Enhanced Memory Systems Inc. 4Mx4, 2 M x 8 ,1 Mx16 16Mbit Enhanced Synchronous DRAM preliminary Data sheet Overview Features • High Perform ance: CAS latency = 2 • P rogram m able Burst Length: 1,2,4,8,full-page • P rogram m able W rap Sequence, S equential or

Contextual Info: 512KX32 16Mbit Enhanced Synchronous DRAM Preliminary Data Sheet Overview Features • High Perform ance: CAS latency = 2 fcK Clock Frequency tcK2 Clock Cycle *AC2 Clock Access Tim e P rogram m able Burst Length: 1,2,4,8,full-page -6 -7.5 -10 Units P rogram m able W rap Sequence, S equential or