LVDS STANDARD 20 PIN Search Results

Contextual Info: CCLD-054X-20-622.080 LVDS Clock Oscillator 5x7mm SMD, 3.3V Model CCLD-054X is a 662.080MHz LVDS Clock Oscillator operating at 3.3Volts. Enable/Disable function used for system testing is offered as a standard feature. Operating Temperature is from -40°C to +85°C with

Contextual Info: CCLD-054X-20-622.080 LVDS Clock Oscillator 5x7mm SMD, 3.3V Model CCLD-054X is a 622.080 MHz LVDS Clock Oscillator operating at 3.3Volts. Enable/Disable function used for system testing is offered as a standard feature. Operating Temperature is from -40°C to +85°C with

"Audio Amplifier"

Contextual Info: EB-1550 ETX Backplane USB2.0 CF 20-pin Power In Serial Port USB2.0 Reset Button LVDS CRT RJ-45 Speaker R Single Board Computer PCI Slot Speaker L PS/2 KB/MS IDE Audio ETX Backplane Specifications *PCI Slot: Standard PCI slot x 1 *LVDS Panel: Supports 24-bit single channel/48-bit dual

SiT8208

Abstract: SiT9121
Contextual Info: SiT9120 Standard Frequency Differential Oscillator The Smart Timing Choice The Smart Timing Choice Features Applications  31 standard frequencies from 25 MHz to 212.5 MHz  LVPECL and LVDS output signaling types  0.6 ps RMS phase jitter random over 12 kHz to 20 MHz bandwidth

Contextual Info: LVDS VCXO SMD-version 2,5 / 3,3V KXO-V63 model frequency range frequency stability incl. temperature stability input voltage and load stability, aging. at -20° ~ +70°C at -40° ~ +85°C 27,0 ~ 700,0 MHz ±25 ppm ~ ±100 ppm ±25 ppm ~ ±100 ppm standard -20° ~ +70°C

KXO-V63

Contextual Info: LVDS VCXO SMD-version 2,5 / 3,3V KXO-V63 model frequency range frequency stability incl. temperature stability input voltage and load stability, aging. at -20° ~ +70°C at -40° ~ +85°C 27,0 ~ 700,0 MHz ±25 ppm ~ ±100 ppm ±25 ppm ~ ±100 ppm standard -20° ~ +70°C

Contextual Info: Standard Products UT200SpWPHY01 SpaceWire Physical Layer Transceiver Advanced Datasheet April 20, 2006 INTRODUCTION FEATURES ‰ 2-bit Serializer/Deserializer SerDes functionality ‰ LVDS physical layer ‰ Data rates to 200 Mbits/sec ‰ Data/Strobe transmit skew <500pS

Contextual Info: LVDS VCXO SMD-version frequency range frequency stability incl. temperature stability input voltage and load stability, aging. at -20° ~ +70°C at -40° ~ +85°C 27,0 ~ 700,0 MHz ±25 ppm ~ ±100 ppm ±25 ppm ~ ±100 ppm standard -20° ~ +70°C available -40° ~ +85°C =KXO-V63T

MAX9377

Abstract: MAX9377EUA MAX9378 MAX9378EUA
Contextual Info: 19-2846; Rev 0; 4/03 Anything-to-LVPECL/LVDS Translators with Pin-Selectable Divide-by-Four Features ♦ Guaranteed 2GHz Switching Frequency ♦ Accept LVDS/LVPECL/Anything Inputs ♦ Pin-Selectable Divide-by-Four Function ♦ 421ps typ Propagation Delays (MAX9377)

MAX9378

Abstract: MAX9377 MAX9377EUA MAX9378EUA
Contextual Info: 19-2846; Rev 1; 7/03 Anything-to-LVPECL/LVDS Translators with Pin-Selectable Divide-by-Four Features ♦ Guaranteed 2GHz Switching Frequency ♦ Accept LVDS/LVPECL/Anything Inputs ♦ Pin-Selectable Divide-by-Four Function ♦ 421ps typ Propagation Delays (MAX9377)

Contextual Info: 19-2846; Rev 1; 7/03 Anything-to-LVPECL/LVDS Translators with Pin-Selectable Divide-by-Four The MAX9377/MAX9378 accept any differential input signal within the supply rails and with minimum amplitude of 100mV. Inputs are fully compatible with the LVDS, LVPECL, HSTL, and CML differential signaling

Contextual Info: SN65LVDS048 LVDS QUAD DIFFERENTIAL LINE RECEIVER SLLS415A – JUNE 2000 – REVISED SEPTEMBER 2000 D D D D D D D D D D D D D D >400 Mbps 200 MHz Signaling Rates Flow-Through Pinout Simplifies PCB Layout 50 ps Channel-to-Channel Skew (Typ) 200 ps Differential Skew (Typ)

metal detector plans

Abstract: SI5334A Si5334C-Axxxxx-GM JESD78 Si5334 SSTL-18 Si5334B-Axxxxx-GM SI5334D
Contextual Info: Si5334 P I N - C ONTR OLLED A N Y - F REQUENCY, A NY - O UTPUT Q U A D C L O C K G ENERATOR Features Applications Si5334 Transparent Top View OEB  Pin Assignments VDDO0  Ordering Information: See page 24. CLK0B  CLK0A  Independent output voltage per

MAX9110

Abstract: MAX9110EKA-T MAX9110ESA MAX9111 MAX9112 MAX9113
Contextual Info: 19-1771; Rev 0; 9/00 Single/Dual LVDS Line Drivers with Ultra-Low Pulse Skew in SOT23 Features ♦ Low 250ps max Pulse Skew for High-Resolution Imaging and High-Speed Interconnect ♦ Space-Saving 8-Pin SOT23 and SO Packages ♦ Pin-Compatible Upgrades to DS90LV017/017A

5962 38535

Contextual Info: Standard Products UT54LVDS218 Deserializer Data Sheet May 24, 2002 FEATURES INTRODUCTION q q q q q 15 to 50MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold sparing all pins Power-down mode <200µW max The UT54LVDS218 Deserializer converts the three LVDS data

54LVDS218

Abstract: UT54LVDS218 LVDS217 marking RAD
Contextual Info: Standard Products UT54LVDS218 Deserializer Data Sheet April, 2002 FEATURES INTRODUCTION q q q q q 15 to 75 MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold sparing all pins Power-down mode <200µW max The UT54LVDS218 Deserializer converts the three LVDS data

LVDS 26 pin connector cable

Abstract: lvds 26 pin lvds cable LVDS connector lvds connector 20 pin LVDS 50 pin LVDS connector 20 pin 50-pin lvds LVDS connector 26 pin lvds 20 pin lcd 20 pin lcd lvds
Contextual Info: PCM-3532 Daughter Board for Gene Series Features LINE_IN External Jack MIC_IN External Jack LINE_OUT External Jack CD_IN Connectors LVDS 26-pin External Connector Two USB External Connectors S-Video Connector RCA External Jack PCM-3524 LVDS Transmitter/Receiver Module

SY58011U

Abstract: SY58012U SY58013U SY58020U SY58021U SY58022U SY89311U SY89830U SY89831U SY89832U
Contextual Info: www.micrel.com Precision Edge DC-to-6GHz Clock Fanout Buffers Smallest Package 16-Pin: 3mm x 3mm MLF™ 8 pin: 2mm x 2mm MLF™ Timing Solutions that Simplify Designs Highest Precision in the Industry ◆ ◆ ◆ ◆ CML Output Swing vs. Frequency Guaranteed ultra-low jitter: <10psPK-PK total jitter

54LVDS218

Abstract: LVDS217
Contextual Info: Standard Products UT54LVDS218 Deserializer Advanced Data Sheet February, 2002 FEATURES INTRODUCTION q q q q q 15 to 75 MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold sparing all pins Power-down mode <200µW max

MAX9126

Contextual Info: 19-1908; Rev 0; 5/01 KIT ATION EVALU E L B A AVAIL Quad LVDS Line Receivers with Integrated Termination Features ♦ Integrated Termination Eliminates Four External Resistors MAX9126 ♦ Pin Compatible with DS90LV032A ♦ Guaranteed 500Mbps Data Rate ♦ 300ps Pulse Skew (max)

circuit diagram of 16-1 multiplexer design logic

Abstract: 10GBASE-ER demultiplexer truth table GR-63-CORE STM-64 stm 64 laser diode 1550 nm
Contextual Info: Data Sheet March 2003 CB64ER-Type 10.3 Gb/s Cooled Lightwave 300-Pin Transponder with 16-Ch. 644 Mb/s Multiplexer/Demultiplexer • ■ ■ ■ ■ ■ Features ■ ■ ■ ■ ■ ■ Supports long-reach 10GBASE-ER optical Ethernet Serial LAN-ER at data rate of 10.3125 Gb/s, with

Pin TO PIN compatible maxim

Contextual Info: 19-1991; Rev 0; 4/01 KIT ATION EVALU E L B A AVAIL Quad LVDS Line Driver Features ♦ Pin Compatible with DS90LV031A ♦ Guaranteed 800Mbps Data Rate ♦ 250ps Maximum Pulse Skew ♦ Conforms to TIA/EIA-644 LVDS Standard ♦ Single +3.3V Supply ♦ 16-Pin TSSOP and SO Packages

Contextual Info: Standard Products UT54LVDS218 Deserializer Advanced Data Sheet October 4, 2001 FEATURES INTRODUCTION q q q q q 15 to 75 MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold sparing all pins Power-down mode <200µW max

Contextual Info: Standard Products UT54LVDS218 Deserializer Advanced Data Sheet October 24, 2001 FEATURES INTRODUCTION q q q q q 15 to 75 MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold sparing all pins Power-down mode <200µW max