SLLU016B Search Results

SLLP101-1

Abstract: cm 68001 VME card cage u2 ic PS2 JACK SN65LVDM31 SN65LVDS31 SN65LVDS32 SN65LVDS32B SLLA054
Contextual Info: Low Voltage Differential Signaling LVDS Evaluation Module (EVM) for Quad Drivers and Receivers User’s Guide 2001 Mixed Signal Products SLLU016B IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

Contextual Info: SN75LVDS31, SN75LVDS9638 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS359C – JUNE 1999 – REVISED JUNE 2001 D D D D D D D Meets or Exceeds the Requirements of ANSI TIA/EIA-644 Standard Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a

Contextual Info: SN75LVDS32, SN75LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS360B – JUNE 1999 – REVISED JUNE 2001 D D D D D D D Meets or Exceeds the Requirements of ANSI TIA/EIA-644 Standard Operates With a Single 3.3-V Supply Designed for Signaling Rate of up to

R-PDSO-G8 FOOTPRINT

Contextual Info: SN65LVDM179, SN65LVDM180, SN65LVDM050, SN65LVDM051 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS SLLS324E – DECEMBER 1998 – REVISED JUNE 2001 D Low-Voltage Differential 50-Ω Line Drivers D D D D D D D D D D and Receivers Signaling Rates up to 500 Mbps

LVDS 20 pin

Abstract: lvdt14
Contextual Info: SN65LVDT14, SN65LVDT41 www.ti.com SLLS530 – APRIL 2002 MEMORY STICK INTERCONNECT EXTENDER CHIPSET WITH LVDS SN65LVDT14—ONE DRIVER PLUS FOUR RECEIVERS SN65LVDT41—FOUR DRIVERS PLUS ONE RECEIVER FEATURES D Integrated 110-Ω Nominal Receiver Line D D

SN65LVDT125

Abstract: SN65LVDS125
Contextual Info: SN65LVDS125 SN65LVDT125 www.ti.com SLLS555A – DECEMBER 2002 – REVISED FEBRUARY 2003 1.5 Gbps LVDS 4x4 CROSSPOINT SWITCH D Switching Non-Blocking Architecture Allows Each Output to be Connected to Any Input Total Jitter < 50ps D D 330 mW When Operating at 1.5 Gbps

Contextual Info: SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER FEATURES DESCRIPTION D Provides Level Translation From LVDS or LVPECL to CML, Repeating From CML to CML D Signaling Rates1 up to 1.5 Gbps D CML Compatible Output Directly Drives

MULTIPLEXER MBPS

Contextual Info: SN65LVDS22, SN65LVDM22 DUAL MULTIPLEXED LVDS REPEATERS SLLS315C– DECEMBER 1998 – REVISED JUNE 2002 D Meets or Exceeds the Requirements of D D D D D D D D D D D ANSI TIA/EIA-644-1995 Standard Designed for Clock Rates up to 200 MHz 400 Mbps Designed for Data Rates up to 250 Mbps

Contextual Info: SN65LVDM1676, SN65LVDM1677 HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVERS SLLS430A – NOVEMBER 2000 – REVISED MAY 2001 D D D D D D D D D D Sixteen Low-Voltage Differential Transceivers Designed for Signaling Rates† Up to 630 Mbps Simplex Point-to-Point and Half-Duplex

Contextual Info: SN65LVDM050-Q1, SN65LVDM051-Q1 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS SGLS128 – JULY 2002 D D D D D D D D D D D D D D D Qualification in Accordance With AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control

Contextual Info: SN65LVDS386/388A/390, SN65LVDT386/388A/390 SN75LVDS386/388A/390, SN75LVDT386/388A/390 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS394D – SEPTEMBER 1999 – REVISED MAY 2001 D D D D D D D D D D D Four ’390 , Eight (‘388A), or Sixteen (‘386) Line Receivers Meet or Exceed the

R-PDSO-G8 FOOTPRINT

Contextual Info: SN55LVDS31, SN65LVDS31, SN65LVDS3487, SN65LVDS9638 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS261I – JULY 1997 – REVISED JUNE 2001 The SN55LVDS31, SN65LVDS31, SN65LVDS3487, and SN65LVDS9638 are differential line drivers that implement the electrical characteristics of low-voltage differential

Contextual Info: SN65LVDS048 LVDS QUAD DIFFERENTIAL LINE RECEIVER SLLS415A – JUNE 2000 – REVISED SEPTEMBER 2000 D D D D D D D D D D D D D D >400 Mbps 200 MHz Signaling Rates Flow-Through Pinout Simplifies PCB Layout 50 ps Channel-to-Channel Skew (Typ) 200 ps Differential Skew (Typ)

schematic diagram 48v dc convertor tl3845

Abstract: sg3524 spice model for pspice schematic diagram 48v ac regulator uc3842 schematic diagram inverter 12v to 24v 30a audio Amp. mosfet 1000 watt 24v dc motor speed control lm324 mini-LVDS and TFT-LCD Timing Controller sg3524 spice model UC1825 spice 500 watt power circuit diagram uc3825
Contextual Info: Selection Guide EIGHTH EDITION Analog/Mixed-Signal Products Designer’s Master Selection Guide August 2002 1996, 1997, 1999, 2000, 2001, 2002 Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications,

Contextual Info: SN65LVDS048A LVDS QUAD DIFFERENTIAL LINE RECEIVER SLLS451B– SEPTEMBER 2000 – REVISED SEPTEMBER 2002 D >400 Mbps 200 MHz Signaling Rates D Flow-Through Pinout Simplifies PCB D D D D D D D D D D D D Layout 50 ps Channel-to-Channel Skew (Typ) 200 ps Differential Skew (Typ)

Contextual Info: SN75LVDS31, SN75LVDS9638 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS359C – JUNE 1999 – REVISED JUNE 2001 D D D D D D D Meets or Exceeds the Requirements of ANSI TIA/EIA-644 Standard Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a

Contextual Info: SN65LVDS047 LVDS QUAD DIFFERENTIAL LINE DRIVER SLLS416A – JUNE 2000 – REVISED MAY 2001 D >400 Mbps 200 MHz Signaling Rates D Flow-Through Pinout Simplifies PCB D D D D D D D D D OR PW PACKAGE (Marked as LVDS047) (TOP VIEW) Layout 300 ps Maximum Differential Skew

Contextual Info: SN65LVDM320 SLLS462 – AUGUST 2001 HIGH-SPEED DIFFERENTIAL 8-BIT REGISTERED TRANSCEIVER D Open-Circuit Differential Receiver Fail Safe FEATURES D 8-Bit Bidirectional Data Storage Register With D D D D D D Assures a Low-Level Output D Reset at Power Up D 12-kV Bus-Pin ESD Protection

Contextual Info: SN65LVDM31 HIGH-SPEED DIFFERENTIAL LINE DRIVER SLLS417C – MARCH 2000 – REVISED MAY 2001 D D D D D D D D Designed for Signaling Rates† Up to 150 Mbps Low-Voltage Differential Signaling With Typical Output Voltage of 700 mV and a 100-Ω Load Propagation Delay Time of 2.3 ns, Typical

SLLA127

Contextual Info: SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558 – DECEMBER 2002 MULTIPOINTĆLVDS LINE DRIVER AND RECEIVER FEATURES D Backplane or Cabled Multipoint Data and D Low-Voltage Differential 30-Ω to 55-Ω Line D Cellular Base Stations D Central-Office Switches

SLLD009

Abstract: SN65LVDS101D R-PDSO-G8 Package
Contextual Info: SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 www.ti.com SLLS516A – AUGUST 2002 – REVISED OCTOBER 2002 2-Gbps DIFFERENTIAL TRANSLATOR/REPEATER FEATURES DESCRIPTION D D D D D These high-speed translators/repeaters were designed for signaling rates up to 2 Gbps to address various

R-PDSO-G5 footprint

Abstract: transistor product line manuals
Contextual Info: SN65LVDS1, SN65LVDS2, SN65LVDT2 HIGH-SPEED DIFFERENTIAL LINE DRIVER/RECEIVERS SLLS373E – JULY 1999 – REVISED MAY 2002 D Meets or Exceeds the ANSI TIA/EIA-644A Standard D Designed for Signaling Rates† up to: D D D D D D D D D D D D – 630 Mbps Drivers

C3-Y

Contextual Info: SN65LVDS386/388A/390, SN65LVDT386/388A/390 SN75LVDS386/388A/390, SN75LVDT386/388A/390 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS394D – SEPTEMBER 1999 – REVISED MAY 2001 D D D D D D D D D D D Four ’390 , Eight (‘388A), or Sixteen (‘386) Line Receivers Meet or Exceed the

Am26LS32 "pin-compatible"

Contextual Info: SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS262L – JULY 1997 – REVISED JUNE 2001 The intended application of these devices and signaling technique is both point-to-point and multidrop one driver and multiple receivers data