LSI LOGIC HYPERPHY Search Results

LSI Rapidchip library

Abstract: LSI LOGIC verilog code for amba ahb bus verilog code for spi4.2 to fifo verilog code AMBA AHB E1110 TR255 TR64 LSI Rapidchip AMBA 3.0 technical summary
Contextual Info: DATASHEET 0.11/0.18 µm ApE1110 Triple-Speed MAC cw101304_ApE1110_1_1 May 2005 DB08-000288-01 This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation.

ddr phy

Abstract: rapidchip LSI coreware library DDR PHY ASIC CW108005 L79301 OC192 LSI Rapidchip Gigablaze serdes CMOS LSI gigablaze serdes
Contextual Info: RapidChip L79301 StreamSlice™ Configurable 10 Gbit/s Platform Advance Datasheet The StreamSlice L79301 Figure 1 is the first platform of the LSI Logic RapidChip configurable-logic family. It greatly reduces the NRE and development costs usually associated with cell-based logic, while

L69301

Abstract: L6930 LSI Rapidchip g12 transistor
Contextual Info: RapidChip L79301 StreamSlice™ Configurable 10 Gbit/s Platform Advance Datasheet The StreamSlice L79301 Figure 1 is the first platform of the LSI Logic RapidChip configurable-logic family. It greatly reduces the NRE and development costs usually associated with cell-based logic, while

LSI Logic ASIC

Abstract: USB Hub LSI coreware library USB PANEL LSI LOGIC
Contextual Info: USB Hub Core Hub Core for Universal Serial Bus Solutions Overview LSI Logic's USB Hub Core, a component of LSI Logic’s comprehensive Universal Serial Bus USB solution set, is a flexible and configurable core that supports additional USB connections within a USB system, enabling the

LSI Rapidchip

Abstract: sfi4.1 CW108005 CW108012 RC11XT531 lsi logic hyperphy
Contextual Info: RapidReady HyperPHY Transceiver CW108005 & CW108012 FEATURES OVERVIEW LSI Logic’s HyperPHY transceiver provides an integration friendly interface for high bandwidth broadband and networking applications. It provides full duplex channels that form serial, point-to-point communication channels at data rates up

mdu 2653

Abstract: mdu 2654 BGA1152 transistor Arm 3055 equivalent Gigablaze serdes CMOS h27 j1 3003 RC1800 A207 resistor R10 J 2995 FC1152
Contextual Info: DATASHEET RapidChip Integrator Platform ASIC Family February 2005 Preliminary DB08-000237-03 This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified either the

ARM926EJ-S Implementation Guide

Abstract: ARM926EJ-S verilog coding for APB bridge state machine for ahb to apb bridge 8 pin AHB ARM926E-JS verilog code for amba ahb master AMBA 2.0 AHB to APB BUS Bridge verilog code AMBA AHB to APB BUS Bridge verilog code ARM926EJ-S jtag
Contextual Info: DATASHEET 0.11 µm Processor System for ARM926EJ-S cw001200_agflxr_2_0 February 2005 Preliminary DB08-000261-01 This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified either the

Contextual Info: LSI LOGIC SYM53C896 Data Sheet SYM53C896 PCI-Dual Channel Ultra2 SCSI Multi-function Controller In the fast-growing server and workstation marketplace, higher levels of performance and integration are required to stay competitive. As a result, data accessibility and the subsequent

ARM1156T2-S

Abstract: AMBA AXI to APB BUS Bridge AMBA AXI to APB BUS Bridge architecture PL022 AXI-64 interface ARM processor data flow PL300 AMBA AHB to AXI AMBA AHB bus protocol ARM1156T2S
Contextual Info: ARM1156T2-S TCM-only Processor with ECC Protection and Reference Design CW001145 FEATURES • 450 MHz timing-closed hardmac OVERVIEW The LSI Logic implementation of the ARM1156T2-S processor for cell-based ASIC provides an integration friendly solution for applications like mass storage

ba05 regulator

Abstract: transistor code ak31 transistor BA29 AU04 3M RC7301 ba05 hp invent j04 RC1800 LSI Rapidchip 2aw22
Contextual Info: DATASHEET RC79301 StreamSlice Platform ASIC July 2003 Preliminary DB08-000235-00 This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified either the functional descriptions, or the electrical and mechanical specifications using

ARM926EJ-S

Abstract: ARM926EJ-S Implementation Guide 011U LogicVision Preliminary Gflx-r RapidChip Cell Technology Data LSI Rapidchip cpdin ARM926EJ-S errata
Contextual Info: DATASHEET 0.11µ ARM926EJ-S Processor cw001124_1_0 October 2004 Preliminary DB08-000262-00 This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified either the functional descriptions, or the electrical and mechanical specifications using

011U

Abstract: LSI coreware library ARM11 lsi logic ARM11 "instruction set summary" armv5te cp14 ARM coprocessor
Contextual Info: DATASHEET 0.11µ ARM966E-S Processor cw001163_1_0 October 2004 Preliminary DB08-000257-00 This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified either the functional descriptions, or the electrical and mechanical specifications using

736-Pin

Abstract: LSI coreware library 64X144
Contextual Info: ADVANCE DATASHEET RC1800 Foundation Slice Family July 2005 The RapidChip RC1800 Foundation Platform ASIC Family, except for the RC1812 slice, is in NO-NEW-DESIGN Status as of July 2005. LSI Logic is not accepting new designs in this slice Family. Information in this datasheet is

ARM926

Abstract: DDR PHY ASIC LSI gigablaze serdes RC1800 LSI Rapidchip DDR1 RAM drawing rc1870 LSI Logic G12
Contextual Info: ADVANCE DATASHEET RC1800 Foundation Slice Family October 2003 DB14-000253-03 This document is advance. As such, it describes a product under development. This information is intended to help you evaluate the product. LSI Logic reserves the right to change or discontinue this proposed product without notice.

LSI coreware library

Abstract: LSI LOGIC OakDSPCore "Hot Plug and Play"
Contextual Info: USB Host Core Host Core for Universal Serial Bus Solutions Overview The USB Host Core, a component of LSI Logic’s comprehensive USB solution set, is a flexible and configurable core that manages and generates the Universal Serial Bus, providing support of USB peripherals in highly integrated embedded systems.

lsi gigablaze transceiver

Abstract: LVTTL25
Contextual Info: DATASHEET RC11XT531 RapidChip Platform ASIC December 2003 Advance DB08-000236-01 This document is advance. As such, it describes a product under development. This information is intended to help you evaluate the product. LSI Logic reserves the right to change or discontinue this proposed product without notice.

SYM53C8XX

Abstract: symbios scsi-1 LSI 2417 SYM53C895
Contextual Info: Lr SYM53C895 Data Sheet SYM53C895 PCI-to-Ultra2 SCSI I/O Processor The SYM53C895 is a PCI-to-Ultra2 SCSI I/O Processor incorporating Universal Low Voltage Differential LVD signaling for SCSI. LSI Logic’ implementation of LVD transceivers is called LVDlink which meets all of the requirements of

gigablaze

Abstract: 11-G02 TRANSISTOR A98 0.18-um CMOS technology multiplexer data sheet LSI gigablaze LSI gigablaze serdes MIPS32 RC11XT404 lsi asic databook RC11XT432
Contextual Info: ADVANCE DATASHEET RapidChip Xtreme Platform ASIC Family July 2004 DB08-000245-00 This document is advance. As such, it describes a product under development. This information is intended to help you evaluate the product. LSI Logic reserves the right to change or discontinue this proposed product without notice.

serdes LSI

Abstract: noise generator gigablaze PCb backplane Layout power supply noise information about bist for uart implementation
Contextual Info: White Paper 6G Data Over Legacy Backplanes LSI’s 6G HyperPHY SerDes Serializer Deserializer enables equipment providers to drive these legacy backplanes at rates greater than 6Gb/s per signal pair. 6 Gb/s (Gigabits per second) applications will begin to dominate the market

SYM53C875

Abstract: SYM8750SP LSI 2417 sym53c8xx sparc mtbf
Contextual Info: Lr Symbios SYM8750SP Data Sheet SYM8750SP PCI-to-Ultra SCSI Host Adapter The SYM8750SP host adapter combines high, Ultra SCSI data transfer rates with the high performance PCI system bus. This Symbios brand host adapter is built around the SYM53C875 PCI-SCSI controller and

Contextual Info: SYM53C896 Data Sheet SYM53C896 PCI-Dual Channel Ultra2 SCSI Multi-function Controller In the fast-growing server and workstation marketplace, higher levels of performance and integration are required to stay competitive. As a result, data accessibility and the subsequent

sparc mtbf

Abstract: ISO-9000 SYM53C860 SYM8600SP 50 PIN SCSI connector symbios
Contextual Info: Lr Symbios SYM8600SP Data Sheet SYM8600SP PCI-to-Ultra SCSI Host Adapter The SYM8600SP host adapter provides an extremely cost-effective solution for systems requiring high, Ultra SCSI data transfer rates on the high-performance PCI system bus. Supporting

SYM8751SPE

Abstract: Beijing Dewing Technology sparc mtbf LVDS scsi connector ISO-9000 PC97 SYM53C875E 68pin TO 50 PIN SCSI connector SYM53C8XX
Contextual Info: Lr Symbios SYM8751SPE Data Sheet SYM8751SPE PCI-to-Ultra SCSI Host Adapter The SYM8751SPE host adapter combines high performance and Ultra SCSI data transfer rates with the speed of a PCI system bus. As part of the Symbios host adapter family built around the

SYM22802

Abstract: SYM53C875 scsi connector 68 pin symbios sparc mtbf 7818 Symbios Semiconductors SYM53C825A SYM53C876 vhdci 68
Contextual Info: Lr Symbios SYM22802 Data Sheet SYM22802 Differential Ultra SCSI Solution The Symbios brand SYM22802 host adapter is a multi-function board providing two independent differential Ultra SCSI channels. Both SCSI channels are identical, offering increased connectivity without utilizing additional