2012 - Not Available
Abstract: No abstract text available
Text: Agilent B4623B Bus Decoder for LPDDR, LPDDR2 , or LPDDR3 Debug and Validation Data Sheet , insight using the B4623B bus decoder for LPDDR, LPDDR2 , or LPDDR3 debug and validation. The B4623B , bus transactions showing associated data bursts, for all LPDDR, LPDDR2 , or LPDDR3 data rates. Valid , length, CAS Latency and CAS Write Latency, Chip Selects) from default LPDDR, LPDDR2 , or LPDDR3 probing configurations and/or DDR Setup Assistant tool to accelerate decode of LPDDR, LPDDR2 , or LPDDR3 bus signals
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B4623B
5991-1064EN
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2010 - Not Available
Abstract: No abstract text available
Text: Agilent Technologies N5413B DDR2 and LPDDR2 Compliance Test Application for Infiniium 9000 and 90000 Series Oscilloscope Data Sheet Test, debug and characterize your DDR2 and LPDDR2 designs quickly and easily The Agilent Technologies N5413B DDR2 and LPDDR2 compliance test application provides a fast and easy way to test, debug and characterize your DDR2 and LPDDR2 designs. The tests , Addendum Rev. 1.1. The tests performed by the LPDDR2 compliance test software are based on the JEDEC(1
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N5413B
N5413B
JESD79-2E
JESD208
DDR2-1066
JESD2092
5989-3195EN
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2011 - MT42L256M32D2
Abstract: MT42L128M32D1 lpddr2 DQ calibration MT42L256M16D1 LPDDR2 SDRAM MT42L128M64D2 MT42L256M64D4 mt42L256m16 LPDDR2 SDRAM micron LPDDR2
Text: . 124 Figure 88: LPDDR2-466 to LPDDR2-1066 Input Signal . 125 Figure 89: LPDDR2-200 to LPDDR2-400 Input Signal , Meg x 32 x 8 banks x 4 die · Device type LPDDR2-S4 , 1 die in package LPDDR2-S4 , 2 die in package LPDDR2-S4 , 3 die in package LPDDR2-S4 , 4 die in package · FBGA "green" package 134-ball FBGA (10mm x , 4Gb: x16, x32 Mobile LPDDR2 SDRAM S4 Features Mobile LPDDR2 SDRAM MT42L256M16D1, MT42L128M32D1
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MT42L256M16D1,
MT42L128M32D1,
MT42L256M32D2,
MT42L128M64D2,
MT42L512M32D4,
MT42L192M64D3,
MT42L256M64D4
09005aef84427aab
MT42L256M32D2
MT42L128M32D1
lpddr2 DQ calibration
MT42L256M16D1
LPDDR2 SDRAM
MT42L128M64D2
mt42L256m16
LPDDR2 SDRAM micron
LPDDR2
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2011 - 216-ball
Abstract: Dual LPDDR2 LPDDR2 SDRAM micron LPDDR2 1Gb Memory MT42L128M64D4 MR63 Micron LPDDR2 lpddr2 168 lp-ddr2 MT42L256M32
Text: . 120 Figure 83: LPDDR2-466 to LPDDR2-1066 Input Signal . 121 Figure 84: LPDDR2-200 to LPDDR2-400 Input Signal , die · Device type LPDDR2-S4 , 1 die in package LPDDR2-S4 , 2 die in package LPDDR2-S4 , 3 die in package LPDDR2-S4 , 4 die in package · FBGA"green" package 134-ball FBGA (11mm x 11.5mm) 134 , containing 2,147,483,648 bits. The LPDDR2-S4 device is internally configured as an eight-bank DRAM. Each of
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MT42L128M16D1,
MT42L64M32D1,
MT42L64M64D2,
MT42L128M32D2,
MT42L256M32D4,
MT42L128M64D4
MT42L96M64D3,
MT42L192M32D3
09005aef83f3f2eb
216-ball
Dual LPDDR2
LPDDR2 SDRAM micron
LPDDR2 1Gb Memory
MR63
Micron LPDDR2
lpddr2 168
lp-ddr2
MT42L256M32
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2011 - SMD MARKING CODE sdp
Abstract: No abstract text available
Text: . 128 Figure 90: LPDDR2-466 to LPDDR2-1066 Input Signal . 129 Figure 91: LPDDR2-200 to LPDDR2-400 Input Signal , x 32 x 8 banks x 4 die 256M64 ⢠Device type â LPDDR2-S4 , 1 die in package D1 â LPDDR2-S4 , 2 die in package D2 â LPDDR2-S4 , 3 die in package D3 â LPDDR2-S4 , 4 die in package D4 â , 4Gb: x16, x32 Mobile LPDDR2 SDRAM S4 Features Mobile LPDDR2 SDRAM MT42L256M16D1, MT42L128M32D1
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MT42L256M16D1,
MT42L128M32D1,
MT42L256M32D2,
MT42L128M64D2,
MT42L512M32D4,
MT42L192M64D3,
MT42L256M64D4,
MT42L384M32D3
09005aef84427aab
SMD MARKING CODE sdp
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2012 - Not Available
Abstract: No abstract text available
Text: . 106 LPDDR2-466 to LPDDR2-1066 Input Signal . 107 LPDDR2-200 to LPDDR2-400 Input Signal , 8 Meg x 16 x 4 banks â 2 x 8 Meg x 16 x 4 banks ⢠Device type â LPDDR2-S4 , 1 die in package â LPDDR2-S4 , 2 die in package ⢠FBGA âgreenâ package â 121-ball FBGA (6.5mm x 8mm) â , random-access memory containing 536,870,912 bits. The LPDDR2-S4 device is internally configured as an four-bank
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512Mb
MT42L32M16D1,
MT42L32M32D2,
MT42L16M32D1
121-ball
134-ball
168-ball
09005aef84d56533
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2013 - LPDDR2 SDRAM micron
Abstract: lpddr2 MT42L256M32D2 LPDDR2 SDRAM micron lpddr2 MT42L128M32D1 micron LPDDR2 X32 35MR11 lpddr2 DQ calibration 216-ball LPDDR
Text: . 125 Figure 90: LPDDR2-466 to LPDDR2-1066 Input Signal . 126 Figure 91: LPDDR2-200 to LPDDR2-400 Input Signal , Meg x 32 x 8 banks x 3 die 192M64 16 Meg x 32 x 8 banks x 4 die 256M64 · Device type LPDDR2-S4 , 1 die in package D1 LPDDR2-S4 , 2 die in package D2 LPDDR2-S4 , 3 die in package D3 LPDDR2-S4 , 4 die , 4Gb: x16, x32 Mobile LPDDR2 SDRAM S4 Features Mobile LPDDR2 SDRAM MT42L256M16D1, MT42L128M32D1
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MT42L256M16D1,
MT42L128M32D1,
MT42L256M32D2,
MT42L128M64D2,
MT42L512M32D4,
MT42L192M64D3,
MT42L256M64D4
09005aef84427aab
LPDDR2 SDRAM micron
lpddr2
MT42L256M32D2
LPDDR2 SDRAM
micron lpddr2
MT42L128M32D1
micron LPDDR2 X32
35MR11
lpddr2 DQ calibration
216-ball LPDDR
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2012 - Not Available
Abstract: No abstract text available
Text: EN LPDDR2-PCM Device LPDDR2 Device LPDDR2 Mobile LPDDR2-Specific Features ⢠⢠â , : 121-Ball ( LPDDR2-PCM and LPDDR2 ) Functional Block Diagram NV-CS# NV-CKE VDD1 LPDDR2âPCM , Product Brief â 121-Ball LPDDR2-PCM and LPDDR2 MCP Features Product Brief LPDDR2-PCM and , Features Figure 1: MCP Block Diagram Micron® LPDDR2-PCM and LPDDR2 components RoHS-compliant, âgreenâ package Shared LPDDR2-PCM and LPDDR2 interfaces Space-saving multichip package Ultra
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121-Ball
MT66R7072A10AB5ZZW
MT66R7072A10ACUXZW
MT66R5072A10ACUXZW
16-bit
09005aef84e25954
121ball
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2012 - Not Available
Abstract: No abstract text available
Text: . 99 LPDDR2-466 to LPDDR2-1066 Input Signal . 100 LPDDR2-200 to LPDDR2-400 Input Signal , banks · Device type LPDDR2-S4 , 1 die in package · FBGA "green" package 121-ball FBGA (6.5mm x 8mm) · , containing 536,870,912 bits. The LPDDR2-S4 device is internally configured as an four-bank DRAM. Each of the , 512Mb: x16 Mobile LPDDR2 SDRAM S4 Features Mobile LPDDR2 SDRAM MT42L32M16D1 Features · Ultra
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512Mb:
MT42L32M16D1
09005aef8467caf2
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2009 - lpddr2
Abstract: micron lpddr2 lpddr2 datasheet micron lpddr2 datasheet Datasheet LPDDR2 SDRAM Jedec JESD209 lpddr2 phy lpddr JESD209-2 LPDDR2 SDRAM memory
Text: Features The LPDDR2 DMC features are: · supports LPDDR SDRAM, LPDDR2-S2 , and LPDDR2-S4 devices · supports the variants (A and B) of LPDDR2 -S2, and LPDDR2-S4 devices · soft macrocell available in , supported, see Table 2-1 on page 2-11 supports 333MHz for LPDDR2-S2 , and LPDDR2-S4 devices. Copyright , memory_cfg and memory_cfg2 Register example, for LPDDR2-S2 devices . 2-32 LPDDR device initialization example . 2-32 LPDDR2-S2
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DMC-342
ID103109)
32-bit
ID103109
lpddr2
micron lpddr2
lpddr2 datasheet
micron lpddr2 datasheet
Datasheet LPDDR2 SDRAM
Jedec JESD209
lpddr2 phy
lpddr
JESD209-2
LPDDR2 SDRAM memory
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2010 - ddr2 ram repair
Abstract: lpddr2 lpddr2 datasheet JESD209 Jedec JESD209 JESD208 intel lpddr2 JESD209-2 ddr ram repair JESD*208
Text: Agilent Technologies N5413B DDR2 and LPDDR2 Compliance Test Application for Infiniium 9000 and 90000 Series Oscilloscope Data Sheet Test, debug and characterize your DDR2 and LPDDR2 designs quickly and easily The Agilent Technologies N5413B DDR2 and LPDDR2 compliance test application provides a fast and easy way to test, debug and characterize your DDR2 and LPDDR2 designs. The tests , Addendum Rev. 1.1. The tests performed by the LPDDR2 compliance test software are based on the JEDEC(1
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N5413B
N5413B
JESD79-2E
JESD208
DDR2-1066
JESD2092
5989-3195EN
ddr2 ram repair
lpddr2
lpddr2 datasheet
JESD209
Jedec JESD209
JESD208
intel lpddr2
JESD209-2
ddr ram repair
JESD*208
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lpddr2
Abstract: lpddr2 datasheet samsung lpddr2 samsung* lpddr2 LPDDR2 1Gb Memory lpddr2 spec lpddr1 samsung toggle mode NAND lpddr2 samsung DDR3L lpddr2
Text: Semiconductor, Inc. 1/? Agenda Industry Trends: IT & Mobile LPDDR2 Effect on Battery Life DDR3 , Industry Trends: IT & Mobile LPDDR2 Effect on Battery Life DDR3 Effect on Energy Saving SSD Effect on , LPDDR2 Effect on Battery Life DDR3 Effect on Energy Saving SSD Effect on Efficiency Virtualization , Memory Bandwidth Wide I/O 12.8GB/s 9.6GB/s LPDDR2 2ch. Serial IO 6.4GB/s LPDDR2 3.2GB/s , Multi Screen `13 `14 Green LPDDR2 Introduction · From Low-density MDDR to higher density LPDDR2
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2012 - Not Available
Abstract: No abstract text available
Text: . 104 LPDDR2-466 to LPDDR2-1066 Input Signal . 105 LPDDR2-200 to LPDDR2-400 Input Signal , 8 Meg x 16 x 4 banks â 2 x 8 Meg x 16 x 4 banks ⢠Device type â LPDDR2-S4 , 1 die in package â LPDDR2-S4 , 2 die in package ⢠FBGA âgreenâ package â 121-ball FBGA (6.5mm x 8mm) â , random-access memory containing 536,870,912 bits. The LPDDR2-S4 device is internally configured as an four-bank
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512Mb
MT42L32M16D1,
MT42L32M32D2,
MT42L16M32D1
121-ball
134-ball
09005aef84d56533
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2012 - lpddr2 DQ calibration
Abstract: micron lpddr2 lpddr2-s4 ADQ28 MT42L128M16D1 LPDDR2 SDRAM micron MT42L64M32D1 MT42L128M32D2 mt42l256m32 LPDDR2 1Gb Memory
Text: . 120 Figure 83: LPDDR2-466 to LPDDR2-1066 Input Signal . 121 Figure 84: LPDDR2-200 to LPDDR2-400 Input Signal , die · Device type LPDDR2-S4 , 1 die in package LPDDR2-S4 , 2 die in package LPDDR2-S4 , 3 die in package LPDDR2-S4 , 4 die in package · FBGA"green" package 134-ball FBGA (11mm x 11.5mm) 134 , containing 2,147,483,648 bits. The LPDDR2-S4 device is internally configured as an eight-bank DRAM. Each of
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MT42L128M16D1,
MT42L64M32D1,
MT42L64M64D2,
MT42L128M32D2,
MT42L256M32D4,
MT42L128M64D4
MT42L96M64D3,
MT42L192M32D3
09005aef83f3f2eb
lpddr2 DQ calibration
micron lpddr2
lpddr2-s4
ADQ28
MT42L128M16D1
LPDDR2 SDRAM micron
MT42L64M32D1
MT42L128M32D2
mt42l256m32
LPDDR2 1Gb Memory
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2010 - mt42l128M32
Abstract: mt42l256m32 MT42L64M32D1 LPDDR2-1066 MT42L256M32D4 MT42L128M32D MT42L128M16D1 MT42L128M64D4 MT42L256M32D MT42L128M32D2
Text: . 120 Figure 83: LPDDR2-466 to LPDDR2-1066 Input Signal . 121 Figure 84: LPDDR2-200 to LPDDR2-400 Input Signal , die · Device type LPDDR2-S4 , 1 die in package LPDDR2-S4 , 2 die in package LPDDR2-S4 , 3 die in package LPDDR2-S4 , 4 die in package · FBGA"green" package 134-ball FBGA (11mm x 11.5mm) 134 , containing 2,147,483,648 bits. The LPDDR2-S4 device is internally configured as an eight-bank DRAM. Each of
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MT42L128M16D1,
MT42L64M32D1,
MT42L64M64D2,
MT42L128M32D2,
MT42L256M32D4,
MT42L128M64D4
MT42L96M64D3,
MT42L192M32D3
09005aef83f3f2eb
mt42l128M32
mt42l256m32
MT42L64M32D1
LPDDR2-1066
MT42L256M32D4
MT42L128M32D
MT42L128M16D1
MT42L256M32D
MT42L128M32D2
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2009 - lpddr2 pcb design
Abstract: lpddr2 samsung lpddr2 lpddr2 datasheet LPDDR2 SDRAM samsung samsung* lpddr2 lpddr2 samsung lp-ddr2 Datasheet LPDDR2 SDRAM "read channel" Samsung
Text: . 9 4 1. Introduction Mobile DRAM consists of mobile SDRAM, mobile DDR SDRAM and LPDDR2. Items Mobile SDR Mobile DDR LPDDR2 Max. Freq. (MHz) 133MHz 200MHz 400/533MHz Max , ] LPDDR2 is fastest in mobile DRAM, and PCB design guidelines is written to use LPDDR2 signals. These guidelines cover Mobile SDR/DDR as well as LPDDR2. 2. PCB Design Guidelines for Signals If one Mobile , In LPDDR2 , DQ net consists of Single line(DQs) and Differential line(DQSs, /DQSs). In mobile SDR/DDR
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40ohm
800Mbps
48ohm
lpddr2 pcb design
lpddr2
samsung lpddr2
lpddr2 datasheet
LPDDR2 SDRAM samsung
samsung* lpddr2
lpddr2 samsung
lp-ddr2
Datasheet LPDDR2 SDRAM
"read channel" Samsung
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2010 - LPDDR2-1066
Abstract: micron lpddr2 lpddr2 DQ calibration LPDDR2 SDRAM micron MT42L128M64D4 lpddr2 MT42L64M64D2 micron LPDDR2 X32 LPDDR2 SDRAM mt42L128M64D
Text: . 102 LPDDR2-466 to LPDDR2-1066 Input Signal . 103 LPDDR2-200 to LPDDR2-400 Input Signal , 8 Meg x 32 x 8 banks x 3 die 8 Meg x 32 x 8 banks x 4 die · Device type LPDDR2-S4 , 2 die in package LPDDR2-S4 , 3 die in package LPDDR2-S4 , 4 die in package · FBGA"green" package 240 , containing 2,147,483,648 bits. The LPDDR2-S4 device is internally configured as an eight-bank DRAM. Each of
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MT42L64M64D2,
MT42L128M64D4,
MT42L96M64D3
240-ball
09005aef84645b7c
LPDDR2-1066
micron lpddr2
lpddr2 DQ calibration
LPDDR2 SDRAM micron
MT42L128M64D4
lpddr2
MT42L64M64D2
micron LPDDR2 X32
LPDDR2 SDRAM
mt42L128M64D
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2011 - lpDDR2 SODIMM
Abstract: No abstract text available
Text: /RLDRAM III, and LPDDR2 SDRAM. Core Specifics Supported Device Family(1) Zynqâ¢-7000(2), Virtex , . DDR3 Component and DIMM, DDR2 Component and DIMM, QDRII+, RLDRAM II, RLDRAM III, and LPDDR2 SDRAM , Vivado Simulators are supported for DDR3 SDRAM, DDR2 SDRAM, QDRII+ SRAM, RLDRAM II, and LPDDR2 SDRAM , Interface Solutions User Guide (UG586) provided with the core. LPDDR2 SDRAM This section discusses the , LPDDR2 SDRAMs. LPDDR2 SDRAM Features ⢠Component support for interface widths up to 32 bits â
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DS176
lpDDR2 SODIMM
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2012 - Not Available
Abstract: No abstract text available
Text: . 127 Figure 90: LPDDR2-466 to LPDDR2-1066 Input Signal . 128 Figure 91: LPDDR2-200 to LPDDR2-400 Input Signal , ¢ Device type â LPDDR2-S4 , 1 die in package â LPDDR2-S4 , 2 die in package â LPDDR2-S4 , 3 die in package â LPDDR2-S4 , 4 die in package ⢠FBGA âgreenâ package â 134-ball FBGA (10mm x 11.5mm , 4Gb: x16, x32 Automotive Mobile LPDDR2 SDRAM Features Automotive Mobile LPDDR2 SDRAM
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MT42L256M16D1,
MT42L128M32D1,
MT42L256M32D2,
MT42L128M64D2,
MT42L512M32D4,
MT42L192M64D3,
MT42L256M64D4
134-ball
168-ball
09005aef84fe5e04
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2013 - Not Available
Abstract: No abstract text available
Text: . 126 Figure 90: LPDDR2-466 to LPDDR2-1066 Input Signal . 127 Figure 91: LPDDR2-200 to LPDDR2-400 Input Signal , ⢠Device type â LPDDR2-S4 , 1 die in package â LPDDR2-S4 , 2 die in package â LPDDR2-S4 , 3 die in package â LPDDR2-S4 , 4 die in package ⢠FBGA âgreenâ package â 134-ball FBGA (10mm , Preliminaryâ¡ 4Gb: x16, x32 Automotive Mobile LPDDR2 SDRAM Features Automotive Mobile
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MT42L256M16D1,
MT42L128M32D1,
MT42L256M32D2,
MT42L128M64D2,
MT42L512M32D4,
MT42L192M64D3,
MT42L256M64D4
134-ball
168-ball
09005aef84427aab)
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2013 - MT42L256M32D2
Abstract: LPDDR2 SDRAM micron MT42L128M32D1 PS 229 ADQ-22 micron lpddr2 MT42L256M32D marking wl4 SMD MARKING code 4N Dual LPDDR2
Text: . 125 Figure 90: LPDDR2-466 to LPDDR2-1066 Input Signal . 126 Figure 91: LPDDR2-200 to LPDDR2-400 Input Signal , Meg x 32 x 8 banks x 3 die 192M64 16 Meg x 32 x 8 banks x 4 die 256M64 · Device type LPDDR2-S4 , 1 die in package D1 LPDDR2-S4 , 2 die in package D2 LPDDR2-S4 , 3 die in package D3 LPDDR2-S4 , 4 die , 4Gb: x16, x32 Mobile LPDDR2 SDRAM S4 Features Mobile LPDDR2 SDRAM MT42L256M16D1, MT42L128M32D1
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MT42L256M16D1,
MT42L128M32D1,
MT42L256M32D2,
MT42L128M64D2,
MT42L512M32D4,
MT42L192M64D3,
MT42L256M64D4
09005aef84427aab
MT42L256M32D2
LPDDR2 SDRAM micron
MT42L128M32D1
PS 229
ADQ-22
micron lpddr2
MT42L256M32D
marking wl4
SMD MARKING code 4N
Dual LPDDR2
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2011 - M1012
Abstract: No abstract text available
Text: . 124 Figure 88: LPDDR2-466 to LPDDR2-1066 Input Signal . 125 Figure 89: LPDDR2-200 to LPDDR2-400 Input Signal , Meg x 32 x 8 banks x 3 die â 16 Meg x 32 x 8 banks x 4 die ⢠Device type â LPDDR2-S4 , 1 die in package â LPDDR2-S4 , 2 die in package â LPDDR2-S4 , 3 die in package â LPDDR2-S4 , 4 die in , 4Gb: x16, x32 Mobile LPDDR2 SDRAM S4 Features Mobile LPDDR2 SDRAM MT42L256M16D1, MT42L128M32D1
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MT42L256M16D1,
MT42L128M32D1,
MT42L256M32D2,
MT42L128M64D2,
MT42L512M32D4,
MT42L192M64D3,
MT42L256M64D4
134-ball
168-ball
216-ball
M1012
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2012 - Not Available
Abstract: No abstract text available
Text: . 103 LPDDR2-466 to LPDDR2-1066 Input Signal . 104 LPDDR2-200 to LPDDR2-400 Input Signal , x 4 banks â 2 x 8 Meg x 16 x 4 banks ⢠Device type â LPDDR2-S4 , 1 die in package â LPDDR2-S4 , 2 die in package ⢠FBGA âgreenâ package â 121-ball FBGA (6.5mm x 8mm) â 134 , CMOS, dynamic random-access memory containing 536,870,912 bits. The LPDDR2-S4 device is internally
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512Mb
MT42L32M16D1,
MT42L32M32D2
121-ball
134-ball
09005aef84d56533
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2013 - MT42L32M32D2
Abstract: micron lpddr2 LPDDR2 SDRAM LPDDR2 SDRAM micron MT42L32M32
Text: . 104 LPDDR2-466 to LPDDR2-1066 Input Signal . 105 LPDDR2-200 to LPDDR2-400 Input Signal , banks · Device type LPDDR2-S4 , 1 die in package LPDDR2-S4 , 2 die in package · FBGA "green" package , , dynamic random-access memory containing 536,870,912 bits. The LPDDR2-S4 device is internally configured as , Preliminary 512Mb Automotive Mobile LPDDR2 SDRAM Features Automotive Mobile LPDDR2 SDRAM
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512Mb
MT42L32M16D1,
MT42L32M32D2,
MT42L16M32D1
09005aef84d56533
MT42L32M32D2
micron lpddr2
LPDDR2 SDRAM
LPDDR2 SDRAM micron
MT42L32M32
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2013 - G2986
Abstract: No abstract text available
Text: G2986 Global Mixed-mode Technology LPDDR2 /LPDDR3 Termination Regulator Features General Description Support 1.2V LPDDR2 /LPDDR3 and DDR IIIL (0.675VTT) Requirements Input Voltage Range: 3V to 5.5V VLDOIN Voltage Range: 1.2V to 3.6V Requires Only 20µF Ceramic Output Capacitance Supports , remote sensing functions and all features required to power the LPDDR2 /LPDDR3 /DDR IIIL VTT bus , Termination LPDDR2 /LPDDR3 Memory Termination SSTLâ2, SSTLâ18 HSTL Termination Ordering Information
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G2986
675VTT)
TDFN2X2-10
G2986
G2986K21U
G2986K21D
TDFN2X2-10
2X2-10
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