LOPS Search Results

M74LS174P

Abstract: 20-PIN 251C
Contextual Info: MITSUBISHI LSTTLs M 74LS174P LOPS W IT H RESET HEX D -l DESCRIPTION The M 7 4L S 17 4P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing 6 D -type edge-triggered flip -flo p circuits w ith common clock input T and direct reset input R D as well

DN74LS109

Abstract: MA161 j-k flip flop clock toggle
Contextual Info: LS TTL DN74LS Series DN74LS109 DN74LS109 J07 Dual J-K P ositive Edge-Triggered F lip-F lops with S et and Reset • Description P -2 D N 7 4 L S 1 0 9 c o n ta in s tw o p o sitive-edge trig g ered J-K flip ­ flo p c irc u its, each w ith in d e p e n d e n t clock-C P, J, K , and

Contextual Info: 5 -ft H JK Hr REV. 6 6 1 0 LOPS 'ON 0 NI MVHQ 1o W. W ft & DESCRIPTION DON NO. DATE 30.Jun.2005 057603 CHANGE TO m BILINGUAL m H.SAKURADA & u APPD. n APPD. a i CHK. DR. T.NOMI YAMA 7 D CM D B M D A M D DM 3* 2 5 1 5 D E M 3 7 * 6 6 6 6 6 -6 -6 (bod?446 465 ^64 764 86^ 4»6 56a

Contextual Info: NXP LoPSTer PQJ7981 ISM/SRD band transceiver Peace of mind with a two-way car key NXP’s two-way solutions drive the next level of car-access applications, adding user feedback and enhanced security capability to the convenience of remote keyless entry.

MPC16S

Abstract: SHC80KP mpc16
Contextual Info: SHC80 B U R R -B R O W N Fast 1C SAMPLE/HOLD AMPLIFIERS FEATURES • 14-PIN DIP PACKAGE • lOpsec ACQUISITION TIM E • C O M P LET E W ITH HOLDING CAPACITOR • ±0.01% ACCURACY DESCRIPTION — » Offset A d j. + 15 V0 C N /C Lo g ic Return Log ic S u p p ly

SJ01

Contextual Info: Ä ft REV. 0065 LOPS ‘ ON 8 ÖNIMVÜQ B DATE 1 5.J un . 2005 DON DR. s REDRAWN na & m A PP D. CHK. N.UCHIYAMA APPD. tiA rtlR o T A B L E 1 ^ ^ D IM EN SIO N (TABLE1) N U M B ER \^ OF CONTACTS^^ ±0. 08 (TABLE1) A ± °. 5 S E C T . (TABLE1) ( S C A L E

Contextual Info: LS TTL DN74LS Series DN74LS74A DN74LS74A Dual D-type Positive Edge-triggered F lip-F lops with S et and Reset • Description P-1 DN74LS74A contains tw o positive-edge triggered D-type flip-flop circuits, each w ith independent clock-CP data-D, and direct-coupled set and reset input term inals.

v520b

Abstract: hef4751 7Z84
Contextual Info: Philips C om ponents-S ignetics TDD1742T Document No. ECN No. Date of Issue February 1987 Preliminary Specification Status Low power frequency synthesizer LOPSY RF Communications G EN ERA L DESCRIPTION The T D D 1742T is a low power, high-performance frequency synthesizer in local oxid a tio n CMOS

DN74LS112

Abstract: MA161
Contextual Info: LS TTL DN74LS Series DN74LS112 DN74LS112 Dual J-K Negative Edge-Triggered F lip-F lops with S et and Reset • P-2 Description D N 7 4 L S 1 1 2 c o n ta in s tw o negative-edge trig g ered J-K flip ­ flo p c irc u its, e ac h w ith in d e p e n d e n t clock-C P , J , K , an d

Contextual Info: LS TTL DN74LS Series DN74LS109 D N 7 4 L S 1 0 9 Dual J-K Positive Edge-Triggered F lip-F lops with S et and Reset • Description P-2 D N74LS109 contains two positive-edge triggered J-K flipflop circuits, each w ith independent clock-CP, J, K, and direct-coupled set and reset input terminals.

HTS-0025

Abstract: hts 0025
Contextual Info: A N A LO G D E V IC E S □ FEATURES Aperture Jitter of lOps Acquisition Time 25ns Output Current ±50mA Slew Rate 250V/|is Ultrahigh Speed Hybrid Track-and-Hold Amplifier HTS-0025 HTS-002S FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Data Acquisition Systems Radar Systems

Contextual Info: 5-R B JK & REV. L01^8 LOPS ‘ON 9 N IM V B a # # fflia (110) 2 27.Deo.2000 46656 3 31.Jui.2003 51320 m K I P3 S D ESCRIP TIO N DON NO. DATE CHANGED TO S EM USU-SCREW RWDRAWN Wm a Hi CHK. SI DR. & W > APPD. APPD. H.SAKURADA Y.NAKAMURA H.SAKURADA T.SUZUK I

Contextual Info: & J& 96 L8 LOPS REV. 'ON 0NIMVHa W 6 5 -RB DATE 3 0 .J u n.2005 NOTE CONNECTOR SECT. DON NO. 057603 — — D ES C R IP TIO N REDRAWN m a DR. w m m APPD. — T.NOMI YAMA 1.APPLI CABLE CABLE DIAMETER SHALL BE 0 11— 0 13. CABLE DIAMETER SHOWN HERE IS WHEN THE SHIELD

Contextual Info: -ON ON I M V B Q -&-#ffll A a LD L^OC P L69 LOPS DATE 2 2 7. Dec . 2000 46656 3 3.J u n.2003 51320 DON I I I4 S NO. CHANGED TO a DR. DESCRIPTION SEM USU -SCREW REDRAWN a is CHK. m & APPD. APPD. H.SAKURADA Y.NAKAMURA H.SAKURADA T.SUZUKI S.NANAO M.MAJIME

Contextual Info: LS TTL DN74LS Series DN74LS114 DN74LS114 ivj'7q_ uSiiq- Dual J-K Negative Edge-Triggered F lip-F lops with Set,Common Reset and Common Clock • Description P-1 D N 74L S 1I4 contains tw o negative-edge triggered J-K flipflop circuits w ith com m on clock-CP and direct-coupled reset

Contextual Info: O rdering num ber : EN821C BTD4M N0.821C SA W O r Silicon Planar Type i Bidirectional Diode F eatu res - Small size and light weight. • DHD type package. A bsolute M axim um R atings atT a = 25°C Peak C urrent Ip f= 120Hz;,pulse width lOps Junction Tem perature

MN74HC174

Abstract: MN74HC174S
Contextual Info: High-Speed CMOS Logic MN74HC Series MN74HC174/ MN74HC174S MN74HC174/MN74HC174S Hex D-Type F lip-F lops with Clear • Description MN74HC174/MN74HC174S contain six hex D-type flip-flop circuits with clear in one chip, and this master/slave flip-flop has common clock and clear. D-input data to be met to set-up time

DN74LS112

Abstract: MA161
Contextual Info: LS T T L DN74LS Series DN74LS112 DN74LS112 107^ Dual J-K Negative Edge-Triggered Flip-F lops with S et and Reset I Description P -2 DN74LS112 contains two negative-edge triggered J-K flip­ flop circuits, each with independent clock-CP, J, K , and direct-coupled set and reset input terminals.

Contextual Info: ^ - 5 9 16 LOPS SYM. DCN DA T E DESCRIPTION NOl DRAWN CHECKED APP' D APP' D T A B LE 1 2 3 . 4 5 6 7 B 9 10 11 12 13 14 15 m C O N T A C T CD OF +do A +0.0 3 4. 4 5 5. 9 5 7. 4 5 8. 9 5 1 0. 4 5 11.95 1 3. 4 5 1 4. 9 5 1 6. 4 5 1 7. 9 5 1 9. 4 5 20. 9 5 22. 4 5

DB-25PAF-N

Contextual Info: 6 8 0 8 LOPS 'ON oniMvaa is-#mm TABLE 2 1 DIMENSION PART ±0-25 B .05 - NUMBE R ±1 A ± 0.13 B DE- 9PAF-N BO. 8 24.99 DE- 9SAF-N 30.8 24.99 DA-15PAF-N 39.1 33.32 DA-15SAF-N 39.1 33.32 DB-25PAF-N 53.0 47.04 DB-25SAF-N 53.0 47.04 D C - 3 7 PA F —N 69.3

mark EAC

Contextual Info: 1 .x z . 'ON 5 -ñ B J K He REV. 3269 LOPS 6 ÖN IMVÜQ - ft±(TABLE2#,B8 CONTACT F I N I SH (S EE T A B L E 2 ) PREFIX ;S&(TABLE1#BS) NO. O F C O N T A C T S ( S E E T A B L E D INSULATOR CON FI 0 U L AT IO N tf>#l TERMINAL PIN SIDE CONTACT ENGAGING LENGTH

komatsu

Abstract: PS-14PE-D4T1-PN
Contextual Info: i 'ON %-n b JK f t REV. 8 9 Z Z LOPS m ON I M V d a DATE 7 17. A p r . 2 0 0 0 DON W M F*3 £ DE S C R I PT I ON NO. R E D RAWN 45946 mm $ M APP D. m i CHK. DR. H.SAKURADA * M APPD. M.SASAKI fi D E S I G N A T I O N • op £ P S —* * P E - D 4 T 1 - P N *

74LS273

Abstract: IC 74LS273
Contextual Info: PANASONIC INDL/ELEK { I O 75 ]>e . bl35flS5 0007500 & 6 9 3 2 8 5 2 PANASONIC I N O L*ELECTR O N IC 72C 0 7 2 00 LS TTL DN74LS5>U—X &&*;• DN74LS273/DN74LS273S DN74LS273 DN74LS273S Octal D-type Flip-F lops (with Reset D N 74LS273/S l i , .& |5 ]& £ }g Wü;*g ' i - t y

2SC381

Abstract: TRANSISTOR 2SC 2SC381-0 2SC381-BN 2SC381-R Na3 sot YT 1617
Contextual Info: ^ ' J D y N P N X \ ^ 5 > ^ 7 ’ \y7 l y - t m h ^ y V 7 , 5 > SILICON NPN EPITAXIAL PLANAR TRANSISTOR . 2SC 381 Unit in mm o PM IP Amplifier Applications - 0.65pP Typ. ) co ‘rt3b/^S/J'^ ^ •' °o •rt>V = lOps (Typ.) Ä K X lf f lf t - C - f : (}pe = 2 9 d B ( f — 1Q7MHZ) (Typ.)