DN74LS5 Search Results

DN74LS51

Contextual Info: DN74LS51 LS T T L DN74LS Series DN74LS51 2 - wide 3-input, 2 - wide 2 - input A N D -O R -IN V E R T G ates P-1 • Description D N 74L S 51 c o n ta in s tw o 2 -in p u t an d tw o 3 -in p u t A N D -O R IN V E R T gates. ■ Features • • • • Low p o w e r c o n su m p tio n Pd = 5.5m W ty p ic a l

DN74LS540

Abstract: DN74LS540S 07274
Contextual Info: PANASONIC INDL/ELEK -CIO 72 D e | ^ 3 2 0 5 2 □□□7272 S T 7 2C 0 7 2 7 2 693 2Qj52 PANASONIC IN PL» ELECTRONIC : L S T T L DN74LS$/'J-v C ü T - r Z -O? DN74LS540/DN74LS540S DN74LS540 DN74LS540S Octal B u ffers and Line D rivers with 3 - state Outputs

DN74LS55

Contextual Info: DN74LS55 LS T T L DN74LS Series DN74LS55 2-w id e 4 - input A N D -O R -INVERT Gates • D escription DN74LS55 contains two 4-input AND-OR-INVERT gates. ■ Features • • Low pow er consum ption Pd = 2.75m W typical High speed ( t pd = 12ns typical) •

AL5V

Abstract: S020D
Contextual Info: PANASONIC INDL/ELEK 6 9 3 £ 3 52 PANASONIC -CIO 75 Ô F p bT32flS2 QÔD7E7S IN D L*ELEC TR O N IC 72C 0 7 2 7 5 LS TTL DN74LS'>U-X - 0 DN74LS541 /DN74LS541S DN74LS541/DN74LS541S Octal B u ffers and Line D riv ers with 3 - sta te Outputs DN 74 LS 541/S |±, f f t * ' f t * L fz 8 Ì ! l f § # i i « t ì i * |i l W A *

Contextual Info: DN74LS55 LS T T L DN74LS Series DN74LS55 2-w id e 4 - input A N D -O R -INVERT Gates • Description DN74LS55 contains two 4-input AND-OR-INVERT gates. ■ Features • • Low pow er consum ption Pd = 2.75m W typical High speed ( t pd = 12ns typical) •

Contextual Info: PANASONIC INDL/ELEK -CIO 75 " •■■: D È I b^BSflSa 00D7E0S 1 . , ■ -': 6932 852 PANASONIC INDL *ELECTRONIC 72C 0 72 05_ O j - W ' / ; LS TTL DN74LS5/U-X DN74LS280/DN74LS280S DN74LS280 DN74LS280S 9-bit Odd/Even P arity G enerators/C heckers D 7 4 L S 2 8 0 /S IÌ, 9 tf-y

Contextual Info: I LS TTL DN74LS Series DN74LS54 DN74LS54 4 - wide A N D - O R - I N V E R T G ates • Description P-1 DN74LS54 contains four 2-input and four 3-input AND-ORINVERT gates. ■ Features • • • • Low power consumption P<j = 4.5mW typical High speed (tPd = 12ns)

DN74LS51

Abstract: MA161
Contextual Info: DN74LS51 LS TTL DN74LS Series DN74LS51 b>o74is,5l 2 - wide 3 - input, 2 - wide 2-input A N D -O R -IN V E R T Gates • Description DN74LS51 contains tw o 2-input and tw o 3 -input AND-ORINVERT gates. ■ Features • • • • Low pow er consum ption P d = 5.5mW typical

MA161

Contextual Info: DN74LS54 LS T T L DN74LS Series DN74LS54 74 LS ^ 4 - wide AND-OR-INVERT Gates • Description DN74LS54 contains four 2-input and four 3-input AND-ORINVERT gates. ^0^ ■ Features • • • • Low power consumption Pa = 4.5mW typical High speed ( tpa = 12ns)

51ti

Abstract: DN74LS541 S020D
Contextual Info: PANASONIC INDL/ELEK 6 9 3 £ 3 52 PANASONIC -CIO 75 Ô F p bT32flS2 QÔD7E7S IN D L * E L E C T R O N IC 72C LS TTL DN74LS&#39;>U-X 07275 - 0 DN74LS541 /DN74LS541S DN74LS541/DN74LS541S Octal B uffers and Line D rivers with 3 - state Outputs DN 74 LS 541/S |±, f f t * ' f t * L fz 8 Ì ! l f § # i i « t ì i * |i l W A *

Contextual Info: I LS TTL DN74LS Series DN74LS51 DN74LS51 2-w id e 3-input, 2-w id e 2-input AND-OR-INVERT Gates • Description P-1 DN74LS51 contains two 2-input and two 3-input AND-ORINVERT gates. ■ Features • Low power consumption P j = 5.5mW typical • High speed (tp<j = 12ns typical)

Contextual Info: LS TTL DN74LS Series DN74LS54 DN74LS54 Ì>N 7 4. L S 4 - wide AND-OR-INVERT Gates • Description P-1 DN 74LS54 contains four 2-input an d four 3-input AND-ORINV ERT gates. ■ Features • • • • Low pow er consum ption P j = 4.5mW typical High speed ( t p d = 12ns)

4H51

Contextual Info: PA N A SO N IC INDL/ELEK -CIO 72 DEJ^bTBSfiSE G0D70ma 7 : ¡iti. • ■>V,s •. av.-r-a si-•*!sv-yJi: >;?•t- ,-ZhVV7. 6 9 3 2 8 52 P ANASONIC I N D L , EL E C I R O N I C . 72C LS TTL DN74LS5>U—X Q7046 P T - 66-21-57 DN74LS148/DN74LS148S D N 7 4 L S 1 4 8 / D N 7 4 L S 1 4 8 S

Contextual Info: LS TTL DN74LS Series DN74LS55 DN74LS55 bN 74IS 55 2 - wide 4 - input AND-OR-INVERT Gates • Description P-1 DN74LS55 contains two 4-input AND-OR-INVERT gates. ■ Features • • • • Low pow er consum ption Pa = 2.75mW typical High speed ( t pd = 12ns typical)

74ls44

Contextual Info: PANASONIC INDL/ELEK ÎICJ 72 69 32 # 52 DE I [^35055 □ DG7Hbli Q P AN AS ONI C I N D L * E L E C T R O N I C f' 72C 07266 LS TTL DN74LS5>U—X DN74LS445/DN74LS445S DN74LS445 DN74LS445S BCD to Decimal Decoders/Drivers • m s D N 74LS445/SI±, * - 7 “ V 3 U 7

Contextual Info: PANASONIC IN DL/ELEK -CIO 75 PANASONIC .6932552 .-’ili-.•_ -*■ DE J INDL . *WE L E C T R ON I C LTBSöSa O Û Q 7 5 7 S □ -72C -072.75 - 0 DN74LS541 /DN74LS541S LS TTL DN74LS&#39;>U-X T D N 5 "5 7 4 L S 5 4 1 / D N 7 4 L S 5 4 1 S Octal Buffers and Line Drivers with 3 -state Outputs

Contextual Info: DE I [^35055 □ DG7Hbli Q f' PANASONIC INDL/ELEK ÎICJ 72 6932#52 PANASONIC INDL*ELECTRONIC 72C 07266 LS TTL DN74LS5>U— X DN74LS445/DN74LS445S DN74LS445 DN74LS445S BCD to Decimal Decoders/Drivers • m s D N 74LS445/SI±, * - 7 “ V 3 U 7 3 - / K7 A ■ œ

74LS273

Abstract: IC 74LS273
Contextual Info: PANASONIC INDL/ELEK { I O 75 ]>e . bl35flS5 0007500 & 6 9 3 2 8 5 2 PANASONIC I N O L*ELECTR O N IC 72C 0 7 2 00 LS TTL DN74LS5>U—X &&*;• DN74LS273/DN74LS273S DN74LS273 DN74LS273S Octal D-type Flip-F lops (with Reset D N 74LS273/S l i , .& |5 ]& £ }g Wü;*g ' i - t y

Contextual Info: 'I LS TTL DN74LS Series DN74LS55 DN74LS55 2 - wide 4 - input AND-OR-INVERT Gates • Description P-1 DN74LS55 contains tw o 4-input AND-OR-INVERT gates. ■ Features • • • • Low power consumption Pd = 2.75mW typical High speed (tpd = 12ns typical)

q72c

Abstract: 07295
Contextual Info: P ANASONIC INDL/ELEK -CIO 75 6932352 PANASONIC ]>~E | ^ 3 2 0 5 2 00072^3 2 INDL*ELECTRONIC 07 ^ ¥{• üf ¿ Sl, 72C 0 7 2 9 3 LS TTL DN74LS5>U—X DN74LS673/DN74LS673S DN74LS673/DN74LS673S 1 6 - bit S h ift R e g is te r s DN74LS673/SÜ, 16fcf-j. hC0&9iJihi) ftCOCÿiJA*. ¡S?iJiii*<0

Contextual Info: DN74LS51 LS TTL DN74LS Series DN74LS51 b>o74is,5l 2 - wide 3 - input, 2 - wide 2-input A N D -O R -IN V E R T Gates • Description DN74LS51 contains tw o 2-input and tw o 3 -input AND-ORINVERT gates. ■ Features • • • • Low pow er consum ption P d = 5.5mW typical

Contextual Info: LS TTL DN74LS Series DN74LS51 DN74LS51 bo 741*51 2-w ide 3-input, 2-w ide 2-input AND-OR-INVERT Gates • Description DN74LS51 contains tw o 2-input and tw o 3-input AND-ORINVERT gates. ■ Features • • • • Low pow er consum ption P d = 5.5mW typical

Contextual Info: DN74LS54 LS TTL DN74LS Series DN74LS54 4 - wide AND-OR-INVERT Gates P-1 • Description DN74LS54 contains four 2-input and four 3-input AND-ORINVERT gates. ■ Features • • Low power consumption Pd = 4.5mW typical High speed (tpci = 12ns) • Low output impedance

DN74LS374

Abstract: t3j5d 74LS374 DN74LS374S
Contextual Info: PANASONIC INDL/ELEK -CIO 72 »e J b13ESSE 0Q0724Ö fl |j*' 6 9 32852 PANASONIC I N D ^ E L E G T R Q N Ï C £ â ^ ^ ^ ; 7 2 C ^ 7 2 4 8 ÿ LS TTL DN74LS5^U~vC DN74LS374/DN74LS374S T - H . DN74LS374 DN74LS374S l o - û i - o S Octal Positive Edge-Triggered D-type Flip-Flops with 3 - state Outputs