LINE CODE MLT SYNCHRONIZATION Search Results

LXT9784

Abstract: FRC34 25Q32BVAIG PIN assignments of UTP cables T61 fuse f4 10BASET LXT9784BC LXT9784BE LED5A led5b
Contextual Info: LXT9784 Low-Power Octal PHY Datasheet The LXT9784 is an eight-port Fast Ethernet PHY Transceiver supporting IEEE 802.3 10Mbps and 100Mbps physical layer applications. It provides both a Reduced Media Independent Interface RMII and a Serial Media Independent Interface (SMII) for switching and other

samsung monitor circuit diagrams

Abstract: Samsung 546 schmit trigger 7286 PIN CONFIGURATION KS9286B KS9286B-L
Contextual Info: KS9286B/KS9286B-L DIGITAL SIGNAL PROCESSOR for CDP DIGITAL SIGNAL PROCESSOR 80-QFP-1420C The KS9286B is a CMOS integrated circuit designed for the Digital Audio Signal Processor for Compact Disc Player. It is a monolithic IC that builts-in 16-bit Digital Analog Convertor, ESP Interface and Digital De-emphasis

s53 optocoupler

Abstract: utc 2411 PEF 82912 SICAN PEF80912 dectlink ntba siemens SCR 1 TIC 126 tic 122 PEF81912
Contextual Info: Da t a Sh e e t , DS 1 , M a rc h 2001 Q-SMINT I 2B1Q Second Gen. Modular ISDN NT Intelligent PEF 82912/82913 Version 1.3 Wi r ed Comm unic at io n s N e v e r s t o p t h i n k i n g . Edition March 2001 Published by Infineon Technologies AG, St.-Martin-Strasse 53,

MLT 22 721

Abstract: MLT 22 634 PLC connect encoder 82562ET AC97 DA82562ET DA82562e stream encoder over lan parallel scrambler 24 bit lfsr
Contextual Info: 82562ET 10/100 Mbps Platform LAN Connect PLC Networking Silicon Datasheet Product Features • ■ ■ ■ ■ ■ ■ ■ IEEE 802.3 10BASE-T/100BASE-TX compliant physical layer interface IEEE 802.3u Auto-Negotiation support Digital Adaptive Equalization control

apc2040

Abstract: SMD MARKING CODE ht1 VOGT M6 smd ht1 vogt transformer 543 Siemens PEB 8091 H marking code HT1 SD ic vogt 543 smd diode v475 VOGT U3
Contextual Info: SIEM EN S ICs for Communications Network Termination Controller 2B1Q NTC-Q PEB 8091 Version 1.1 PEF 8091 Version 1.1 D a ta s h e e t 10.97 DS 1 IOM , IOM®-1, IOM®-2, SICOFI®, SICOFI®-2, SICOFI®-4, SICOFI®-4|iC, SLICOFI®, ARCOFI® , ARCOFI®-BA,

s53 optocoupler

Abstract: PEF82912 NTC Siemens m 822 PEF 2091 F V5.3 PEF 2091 N V5.3 PEF 4265 PEF80912 PEF80913 PEF81912 PEF81913
Contextual Info: Da t a Sh e e t , DS 1 , M a rc h 2001 Q-SMINT IX 2B1Q Second Gen. Modular ISDN NT Intelligent eXtended PEF 81912/81913 Version 1.3 Wi r ed Comm unic at io n s N e v e r s t o p t h i n k i n g . Edition March 2001 Published by Infineon Technologies AG,

EP82562G

Abstract: 82562e 82562ET 82562G 82562GT
Contextual Info: 82562G 10/100 Mbps Platform LAN Connect PLC Networking Silicon Datasheet Product Features • ■ ■ ■ ■ ■ ■ ■ IEEE 802.3 10BASE-T/100BASE-TX compliant physical layer interface IEEE 802.3u Auto-Negotiation support Digital Adaptive Equalization control

EP82562GT

Abstract: MLT 22 831 82562GT 82562ET LU82562GT MLT 22 542
Contextual Info: 82562GT 10/100 Mbps Platform LAN Connect PLC Networking Silicon Datasheet Product Features • ■ ■ ■ ■ ■ ■ ■ ■ IEEE 802.3 10BASE-T/100BASE-TX compliant physical layer interface IEEE 802.3u Auto-Negotiation support Digital Adaptive Equalization control

Q67101-H6587

Abstract: asm 1011 W25 smd AD11 AE10 AF10 AC10 AC11 AD10 PXB4310
Contextual Info: ICs for Communications ATM Switching Matrix PXB 4310 Version 1.1 Preliminary Data Sheet 12.97 DS 2 PXB 4310 Revision History: Current Version: 12.97 Previous Version: Preliminary Data Sheet 08.95 V 1.1 Functional Update Page Page (in previous (in current

PMC-920404

Abstract: 0X00 PM5345 marking ad802 PM5712B
Contextual Info: PM5345 S/UNI-155 DATA SHEET PMC-930305 ISSUE 4 SATURN USER NETWORK INTERFACE PM5345 S/UNI-155 SATURN USER NETWORK INTERFACE TELECOM STANDARD PRODUCT DATA SHEET ISSUE 4: JUNE 1998 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

British Telecom

Abstract: circuit diagram for micro controller based caller INFINEON package tqfp PART MARKING PSB4600 siemens PSB4600 adapter rs232 diagram c166 programming c C541U ISDN TE adapter chips Intel SCOUT Chipset
Contextual Info: ICs for Communications ISDN Data Access Solution Guide for ISDN Data Access Solution Guide 10.99 DS 2 Revision History: Current Version: 10.99 Previous Version: Page Page in previous (in current Version Version) Subjects (major changes since last revision)

Contextual Info: S ta n d a r d P r o d u c t PM I I PMC-Sierra, Inc. 1^^ P M 5 3 4 5 S /U N I ISSUE 3 SATURN USER N E TWORK INTERFACE PM5345 US E R SATURN NETWORK INTERFACE I ssue 3 February, PMC-Sierra, Inc. 1995 8501 Commerce Court Burnaby, BC Canada V5A 4N3 604 668 7300

82371SB

Contextual Info: intei PRELIMINARY 82371FB PIIX AND 82371 SB (PIIX3) PCI ISA IDE XCELERATOR — Independently Programmable for Edge/Level Sensitivity Bridge Between the PCI Bus and ISA Bus PCI and ISA Master/Slave Interface — PCI from 25-33 MHz — ISA from 7.5-8.33 MHz

APIC- S06

Abstract: 82371 430fx 82371FB 82371SB
Contextual Info: intei PRELIMINARY 82371FB PIIX AND 82371 SB (PIIX3) PCI ISA IDE XCELERATOR — Independently Programmable for Edge/Level Sensitivity Bridge Between the PCI Bus and ISA Bus PCI and ISA Master/Slave Interface — PCI from 25-33 MHz — ISA from 7.5-8.33 MHz

intel 430FX

Abstract: PIIX3 430FX 74ALS00 82371FB 82371SB 82C54 82C59 ALS244
Contextual Info: E n n n n n n n n 82371FB PIIX AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR Bridge Between the PCI Bus and ISA Bus PCI and ISA Master/Slave Interface  PCI from 25–33 MHz  ISA from 7.5–8.33 MHz  5 ISA Slots Fast IDE Interface  Supports PIO and Bus Master IDE

sxe capacitor NCC

Contextual Info: Data Sheet February 1998 microelectronics group Lucent Technologies Bell Labs Innovations T7234 Single-Chip NT1 SCNT1 Euro-LITE Transceiver Features Description • U- to S/T-interface conversion for ISDN basic rate (2B+D) systems — Integrated U- and S/T-interfaces

S5L9276X01

Abstract: dump HD4 A2 8H26 DA03 DA11 KM44V4100C S5L9276 hifu MLRB b00xxx
Contextual Info: S5L9276 PRELIMINARY SPEC OPTICAL CD MP3 SYSTEM INTRODUCTION 64-LQFP-1010 S5L9276 is a single chip ISO/IEC 11172-3 Layer III audio decoder, capable of decoding compressed elementary bit stream as specified in ISO/IEC standard. As a decoder for the DISC-MAN, it can provide you more small and cheaper

coach 12

Abstract: "LDAP" "OSPF" "Spanning Tree" "routing tables"
Contextual Info: White Paper Quality of Service In Frame-Switched Networks Bursty, high-bandwidth, realtime and mission-critical applications are driving the need for better differentiation of services in the campus network beyond that provided by traditional best-effort services. Until recently, ATM

4-20ma ADC INPUT

Abstract: irs5 motorola op amp MAX1463 MAX1463AAI MAX1463CAI MAX1463EAI "pressure sensor Signal Conditioning" MLT 22 545
Contextual Info: 19-2549; Rev 0a; 11/04 Low-Power Two-Channel Sensor Signal Processor The MAX1463 is a highly integrated, low-power, twochannel sensor signal processor optimized for industrial and process control applications such as pressure sensing and compensation, RTD and thermal-couple

Motorola TE 2482

Abstract: data sheet IC 7400 IC 7400 pin diagram HP 3070 series 3 Manual zener Diode B23 data sheet ic 7495 B26 ZENER DIODE Philips 2222-370 KU 601 R64T
Contextual Info: Advisory November 1998 T7234, T7237, and T7256 Compliance with the New ETSI PSD Requirement Refer to the T7234, T7237, and T7256 ISDN transceiver data sheets. Telecommunication Standard The European Telecommunications Standards Institute (ETSI) has identified a change in the requirement of

82441fx

Contextual Info: PRELIMINARY intel INTEL 440FX PCISET 82441FX PCI AND MEMORY CONTROLLER PMC AND 82442FX DATA BUS ACCELERATOR (DBX) Supports the Pentium Pro Processors at Bus Frequencies Up To 66 Mhz — Supports 32-Bit Addressing — Optimized in-Order and Request Queue

DBX 202

Abstract: MD7144 HD2554 440FX 82371SB 82441FX 82442FX AD11 AD12 intel 440FX
Contextual Info: E PRELIMINARY INTEL 440FX PCISET 82441FX PCI AND MEMORY CONTROLLER PMC AND 82442FX DATA BUS ACCELERATOR (DBX) Supports the Pentium Pro Processors at Bus Frequencies Up To 66 Mhz  Supports 32-Bit Addressing  Optimized in-Order and Request Queue  Full Symmetric Multi-Processor

Contextual Info: m i c ro e I e c t ro n i c s g r o u p Data Sheet February 1998 Lucent Technologies Bell Labs Innovations T7237 ISDN U-lnterface Transceiver Features Description • U-interface for ISDN basic rate 2B+D systems — Serial microprocessor and time-division multi­

bridge 3417

Abstract: 430TX Configuration 82443bx 82443bx host bridge datasheet
Contextual Info: Register Description Register Description 3 The 82443BX contains two sets of software accessible registers, accessed via the Host CPU I/O address space: 1. Control registers that are I/O mapped into the CPU I/O space. These registers control access to PCI and AGP configuration space.