LH5494 Search Results

MD 7144

Abstract: lh5494
Contextual Info: LH5494/ 4K X9 Serial-toParallel FIFO input and output ports respectively. However, these ‘clocks' also may be aperiodic, asynchronous ‘demand’ signals: they do not need to be synchronized with each other in any way. Almost all control input signals and

organizational structure samsung

Abstract: CYPRESS SAMSUNG CROSS REFERENCE DALLAS cross reference VITELIC MK4501 ic cross reference book CY7C408 mosel KM75C02
Contextual Info: FIFO Cross Reference FIFO CROSS REFERENCE ORGANIZATIONAL STRUCTURE SHARP MODEL * COMPETITIVE VENDOR 256 X 36 X 2 LH5420 LH5481 64 X 8 64 X 9 LH5491 4,096 X 9 4,096 X 9 4,096 X 9 1,024 X 9 2,048 X 9 X LH5493 LH5494 LH5496/96H 512 X 9 4.096 LH5492 9 LH5497/97H

Contextual Info: LH5494 FEATURES • Fast Cycle Times: 25/30/35 ns Frequency: 40/33/28.5 MHz • Serial Data In; Parallel Data Out • Serial Output for Cascading Input Register • Two Read Enable Inputs and One Write Enable Input, Sampled on Rising Edge of the Appropriate

Contextual Info: LH5494 FEATURES • Fast Cycle Times: 30/35 ns Frequency: 33/28.5 MHz • Serial Data In; Parallel Data Out • Serial Output for Cascading Input Register • Two Read Enable Inputs and One Write Enable Input, Sampled on Rising Edge of the Appropriate Clock

lh57257

Abstract: IR2E31 IR2E01 IR2C07 IR2E27 IR2E24 IR2E19 IR2E31A IR3n06 IR2E02
Contextual Info: Index Model No. ARM7D CPU Core Bi-CMOS 1 27 40,42 _ _ CMOS CMOS CMOS CMOS CMOS 4A 5A 8 A AH D ID1 Series ID2 Series 40,42 40.42 40,42 40,42 40 B ü.’1*"! 14,15 14 m IR2339 IR2403 IR2406 IR2406G IR2410 IR2411 IR2415 IR2419 IR2420 IR2422 IR2425 IR2429

Contextual Info: MEMORIES ★Under development • FIFO M emories Capacity Conlfeuralion word* x bits 64x8 0.5k 64 x 9 4.5k 512x9 1k x 9 9k 512 x 18 2k x 9 18k 1k x 18 256 x 36 x 2 4k x 9 36k 1k x 36 72k QFJ=PLCC 8k x 9 Modal No. LH5481D/U-25 LH5481D/U-35 LH5491D/U-25 LH5491D/U-35

Contextual Info: MEMORIES FIFO M emories ★Under developm ent Type Capacity Configuration Operating frequency MHz MAX. Model No. 25 —i 35 Access time(ns) 15 20 25 35 Package SKDIP QFJ 28 28 28 28 28 28 32 — 28 28 32 28 32 28 32 28 32 50 DIP LH5481 LH5491 j — LH5496

Contextual Info: MEMORIES • FIFO Memories Capacity Configuration words x bits Model No. LH5481D/U-25 Operating frequency (MHz) MAX. 25 Access time (ns) MAX. - Cycle time (ne) MIN. - Supply current operstlng/standby (mA) MAX. Supply voltage (V) 4 5/— Package 28S K -D IP /