LC1 E18 01 Search Results

UPD 552 C

Abstract: LC1 D12 P7 XC2000 XC3000 XC4000 XC5200 XC5202 XC5204 XC5206 XC5210
Contextual Info: XC5200 Field Programmable Gate Arrays  June 1, 1996 Version 4.0 Preliminary Product Specification Features • Fully supported by XACTstep Development System - Includes complete support for XACT-Performance™, X-BLOX™, Unified Libraries, Relationally Placed

NS9360

Abstract: netarm 40 SOT-353 c15 Digi m10 BIT1502 arm926ejs bootstrap ARM926EJ-S BGA272 MAX811 spi master
Contextual Info: NS9360 Datasheet The Digi NS9360 is a single chip 0.13 m CMOS network-attached processor. The CPU is the ARM926EJ-S core with MMU, DSP extensions, Jazelle Java accelerator, and 8 kB of instruction cache and 4 kB of data cache in a Harvard architecture. The NS9360 runs up to 177 MHz, with a 88 MHz

AS 108-120

Abstract: LC1 D12 10 K1882 nec d 882 p datasheet XAPP 138 data XC5200 XC3000 XC4000 XC5202 XC5204
Contextual Info: XC5200 Series Field Programmable Gate Arrays R November 5, 1998 Version 5.2 7* Product Specification Features - • Low-cost, register/latch rich, SRAM based reprogrammable architecture - 0.5µm three-layer metal CMOS process technology - 256 to 1936 logic cells (3,000 to 23,000 “gates”)

AS 108-120

Abstract: LC1 D12 10 LC1 D18 wiring diagram X4963 LC1 D12 P7 XC3000 XC4000 XC5200 XAPP 017 XC5204
Contextual Info: 1 1 XC5200 Series Field Programmable Gate Arrays  December 10, 1997 Version 5.0 1 4* Features Product Specification • • Low-cost, process-optimized, register/latch rich, SRAM based reprogrammable architecture - 0.5µm three-layer metal CMOS process technology

tag 8852

Abstract: LASCR x1cv Shortform Transistor Datasheet Guide tms34020 TMS320C80 GACA J-D1N 1/TRIAC tag 8852
Contextual Info: TMS320C80 MVP Parallel Processor User’s Guide 1995 Digital Signal Processing Products Printed in U.S.A., March 1995 SPRU110A TMS320C80 (MVP) Parallel Processor 1995 User’s Guide TMS320C80 (MVP) Parallel Processor User’s Guide SPRU110A March 1995 Printed on Recycled Paper

Contextual Info: Elan SC400 and ElanSC410 AMDÎ1 Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers DISTINCTIVE CHARACTERISTICS Elan™SC400 and ElanSC410 Microcontrollers • ■ ■ Standard PC/AT system logic PICs, DMACs, timer, RTC - DOS, ROM-DOS, Windows, and industrystandard BIOS support

Contextual Info: Elan SC400 and ElanSC410 AMDÎ! Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers DISTINCTIVE CHARACTERISTICS Elan™SC400 and ElanSC410 Microcontrollers • ■ ■ Standard PC/AT system logic PICs, DMACs, timer, RTC - DOS, ROM-DOS, Windows, and industrystandard BIOS support

BGA292

Abstract: CS10 CS11 E86TM ELANSC400 ELANSC410 MA11 SC400 SD15 UART 16550A
Contextual Info: Élan SC400 and ÉlanSC410 Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers DISTINCTIVE CHARACTERISTICS Élan™SC400 and ÉlanSC410 Microcontrollers • E86TM family of x86 embedded processors – Offers improved time-to-market, software migration, and field-proven development tools

CQL10

Abstract: dsc 8d15 8D15-8DO amd elan amd elan sc400 and am386-dx 40 cq met t2a 250 micron 80l power resistor tt25 CAPACITORS ELANSC400
Contextual Info: Elan SC400 and ElanSC410 AMDÌ1 Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers DISTINCTIVE CHARACTERISTICS • Elan™SC400 and ElanSC410 Microcontrollers ■ ■ - DOS, ROM-DOS, Windows, and industrystandard BIOS support E86™ family of x86 embedded processors

gc 7137 ad

Abstract: transistor c5200 c5200 transistor TTC 5200 C5200 LC1 D18 P7 HC 148 TRANSISTOR ATIC 164 D2 44 pin
Contextual Info: £ XILINX XC5200 Series Field Programmable Gate Arrays Novem ber 5, 1998 Version 5.2 Product Specification Features - • Low-cost, register/latch rich, SRAM based reprogram m able architecture - 0.5|j.m three-layer metal CMOS process technology - 256 to 1936 logic cells (3,000 to 23,000 “gates”)

TRXD12

Abstract: cg3 g1 608 S1C8F626 lc1 d18 bl 3448-7950 cdr64 seiko epson 7920 S1C88348 S1C88649 lcdc
Contextual Info: CMOS 8-BIT SINGLE CHIP MICROCOMPUTER S1C8F626 Technical Manual NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any

ek070

Abstract: CDR03 receiver cdr64 S1C88348 S1C88650
Contextual Info: CMOS 8-BIT SINGLE CHIP MICROCOMPUTER S1C88650 Technical Manual S1C88650 Technical Hardware NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any

Contextual Info: JIXILINX XC5200 Field Programmable Gate Arrays June 1, 1996 Version 4.0 Preliminary Product Specification Features • Fully supported by XACTsfep Development System - Includes complete support for XACT-Performance™, X-BLOX™, Unified Libraries, Relationally Placed

XCS200 FPGA

Contextual Info: HXILINX XC5200 Series Field Programmable Gate Arrays December 10, 1997 Version 5.0 Product Specification Features • • Low-cost, process-optimized, register/latch rich, SRAM based reprogrammable architecture - 0.5pm three-layer metal CMOS process technology

7448 bcd to seven segment decoder

Abstract: 7448 seven segment display data sheet datasheet 7448 BCD to Seven Segment display CI 7448 The 555 Timer Applications Sourcebook interfacing cpld xc9572 with keyboard SERVICE MANUAL OF FLUKE 175 100352 The Transistor Manual Japanese 1993 xc95144 pinout
Contextual Info: The Programmable Logic Data Book July 1998 R , XILINX, XACT, XC2064, XC3090, XC4005, XC-DS501, FPGA Architect, FPGA Foundry, NeoCAD, NeoCAD EPIC, NeoCAD PRISM, NeoROUTE, Plus Logic, Plustran, P+, Timing Wizard, and TRACE are registered trademarks of Xilinx, Inc.

SERVICE MANUAL OF FLUKE 175

Abstract: SHARP IC 701 I X11 dot led display large size with circuit diagram IR power mosfet switching power supply The 555 Timer Applications Sourcebook interfacing cpld xc9572 with keyboard distributed control system of power plant 100352 XC3090-100PG175 xc95144 pinout
Contextual Info: R , XILINX, XACT, XC2064, XC3090, XC4005, XC-DS501, FPGA Architect, FPGA Foundry, NeoCAD, NeoCAD EPIC, NeoCAD PRISM, NeoROUTE, Plus Logic, Plustran, P+, Timing Wizard, and TRACE are registered trademarks of Xilinx, Inc. , all XC-prefix product designations, XACTstep, XACTstep Advanced, XACTstep Foundry, XACT-Floorplanner,

TXN612

Abstract: MT 8222 t1e8 AMI 8531
Contextual Info: + DS32506/DS32508/DS32512 6-/8-/12-Port DS3/E3/STS-1 LIU www.maxim-ic.com FEATURES GENERAL DESCRIPTION Pin-Compatible Family of Products Each Port Independently Configurable Receive Clock and Data Recovery for Up to 457 meters 1500 feet of 75Ω Coaxial Cable

PM RGL6

Abstract: DS32506 DS32506N DS32508 DS32508N DS32512 DS32512N intel 8361 TR-54
Contextual Info: + DS32506/DS32508/DS32512 6-/8-/12-Port DS3/E3/STS-1 LIU www.maxim-ic.com FEATURES GENERAL DESCRIPTION Pin-Compatible Family of Products Each Port Independently Configurable Receive Clock and Data Recovery for Up to 457 meters 1500 feet of 75Ω Coaxial Cable

t1e8

Abstract: R18A3
Contextual Info: + DS32506/DS32508/DS32512 6-/8-/12-Port DS3/E3/STS-1 LIU www.maxim-ic.com FEATURES GENERAL DESCRIPTION Pin-Compatible Family of Products Each Port Independently Configurable Receive Clock and Data Recovery for Up to 457 meters 1500 feet of 75Ω Coaxial Cable

Contextual Info: + DS32506/DS32508/DS32512 6-/8-/12-Port DS3/E3/STS-1 LIU www.maxim-ic.com FEATURES GENERAL DESCRIPTION Pin-Compatible Family of Products Each Port Independently Configurable Receive Clock and Data Recovery for Up to 457 meters 1500 feet of 75Ω Coaxial Cable

T1E8

Contextual Info: + DS32506/DS32508/DS32512 6-/8-/12-Port DS3/E3/STS-1 LIU www.maxim-ic.com FEATURES GENERAL DESCRIPTION Pin-Compatible Family of Products Each Port Independently Configurable Receive Clock and Data Recovery for Up to 457 meters 1500 feet of 75Ω Coaxial Cable

t1e8

Abstract: DS32506N
Contextual Info: + DS32506/DS32508/DS32512 6-/8-/12-Port DS3/E3/STS-1 LIU www.maxim-ic.com FEATURES GENERAL DESCRIPTION Pin-Compatible Family of Products Each Port Independently Configurable Receive Clock and Data Recovery for Up to 457 meters 1500 feet of 75Ω Coaxial Cable

SA4-13

Abstract: SA5-27 RHS25
Contextual Info: Device Advisory October 1999 TFRA08C13 Device Advisory for Version 2.0 of the Device Introduction This advisory refers to version 2.0 of the TFRA08C13 Octal T1/E1 Framer. This advisory addresses the timing issue of the microprocessor interface when FDL registers are accessed. This advisory also introduces guidelines for interfacing TFRA08C13 with processors of the Motorola* M68000 family.

Contextual Info: group Advance Data Sheet May 1998 Lucent Technologies Bell Labs Innovations T7633 DualT1/E1 3.3 V Short-Haul Terminator Features Alarm reporting and performance monitoring per AT&T, ANSI, and ITU-T standards. T heT7633 Dual T1/E1 Terminator consists of two