LAYOUT Search Results

Contextual Info: 54AC11109, 74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0066— D2957, M ARCH 1987— REVISED M ARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11109 . . . J PACKAGE 74AC11109 . . . D OR N PACKAGE TOP VIEW

Contextual Info: 54AC11032, 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES TI0060— D2957, JULY 1987— REVISED MARCH 1990 54A C 11032 . . . J PACKAGE 74A C 11032 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin V c c and GND Configurations to

Contextual Info: 54AC11021,74AC11021 DUAL 4-INPUT POSITIVE-AND GATES _ D2957. JULY 1987 - REVISED APRIL 1993 54AC11021 . . . J PACKAGE 74AC11021 . . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations

Contextual Info: 54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES D2957, JUNE 1987 - REVISED APRIL 1993 54AC11002 . . . J PACKAGE 74AC11002 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin Vcc and GND Configuration Minimizes High-Speed Switching Noise

Contextual Info: REFERENCE DATA KV1 8 4 5K S P E C I F I C A T I ON •TABLE OF CONTENTS 1. PURPOSE 2. T O K O PART NUMBER 3. APPLICATIONS 4. STRUCTURE 5. PA CKAGE OUTLINE 6. PIN LAYOUT 7. PACKAGE OUTLINE D I M E N S I O N S / S IG N A T U R E Drawn By MARKING 8. ABSOLUTE MAXIMUM RATINGS

Contextual Info: 54ACT11002,74ACT11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCAS003A - D2957, JUNE 1987 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-PIn V^c and GND Configurations Minimize High-Speed Switching Noise

Contextual Info: REFERENCE DATA] - K V 14 7 0 S P E C I F I C A T I ON T AB LE OF C O N T E N T S 1. PURPOSE 2 . TOKO PART NUMBER 3. APPLICATIONS 4. STRUCTURE 5. PACKAGE OUTLINE 6. PIN LAYOUT 7. PACKAGE OUTLINE DIM ENSIONS/ S IG N ATU RE D ATE Drawn By MARKING

321f

Contextual Info: Catalog 1308389 BUCHANAN Terminal Blocks Revised 12-02 TWO-PIECE TERM INAL BLOCK CONNECTORS Straight, Open End Headers, 7.62 mm Centerline Color-Green UL Rating-3 0 0 V, 15 A Z.91 .115 ' J U u 1.U 7,62 C39 R ecom m ended PC Board Layout .300 0 1 .4 o 7.62

D2957

Contextual Info: 54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS I_ • ■ I I I D2957, JULY 1987-R E V IS E D APRIL 1993 * 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations

74AC11520

Contextual Info: 54AC11520,74AC11520 8-BIT IDENTITY COMPARATORS D2957, JULY 1987 - REVISED APRIL 1993 54AC11520 . . . J PACKAGE 74AC11S20. . . DW OR N PACKAGE TOP VIEW Compares TVvo 8-Bit Words Flow-Through Architecture Optimizes PCB Layout Center-PIn Vcc and GND Configurations

2a117

Contextual Info: 54AC11158, 74AC11158 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS TI010&— D 2957 JULY 1969— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11158 . . . J PACKAGE 74AC11158 . . . DW OR N PACKAGE TOP VIEW Center-Pin V c c and GND Configurations to

Contextual Info: 4 THIS DRAWING IS UNPUBLISHED. COPYRIGHT 3 RELEASED BY TYCO ELECTRONICS CORPORATION. FOR PUBLICATION - - - ALL RIGHTS RESERVED. D 4 .5 2 [.178] 0 .76 [.030] NOM ACTUTATION DISTANCE C 3.56 B 01 .09 2 .5 4 2 PLACES PCB A HOLE LAYOUT SCALE 5:1 LOC DIST AD 00

Contextual Info: BUCHANAN Catalog 1308389 Terminal Blocks Re vised 12-02 TW O-PIECE TERMINAL B LO C K CO NN EC TO RS Straight Header w/Locking Screw Flange, 5.0 mm Centerline, Color - Green Recommended PC Board Layout 5.00 UL Rating -300 V, 15 A No. of Positions Dim. A 2 5.0 [0.197]

D3348

Abstract: 74AC11151
Contextual Info: 74AC11151 1-0F-8 DATA SELECTOR/MULTIPLEXER D3348, JUNE 1989 - REVISED APRIL 1993 * 8-Llne to 1-Llne Multiplexers Can Perform as Boolean Function Generators, Parallel-to-Serlal Converters, or Data Source Selectors * Flow-Through Architecture Optimizes PCB Layout

Contextual Info: 74AC11204 HEX INVERTER/CLOCK DRIVER D3427, O C TO B ER 1989 DW OR N PACKAGE Low-Skew Propagation Delay Specifications for Clock Driver Applications TOP VIEW 1Y[ 1 2Y [ 2 3Y [ 3 Flow-Through Architecture Optimizes PCB Layout * * * Package Options Include Plastic “Small

Contextual Info: REFERENCE DATA Production Standard Note TK111XXM Table of C ontents 1 . S tr u c tu r e /F e a tu r e 2 . E lectrical C haracteristics Specification for S ta n d ard Device 3 . P in Layout 4 . T est C ircuit 5 . Block D iagram D efinition of Term s Sensor C ircuit

Contextual Info: KV 1 8 4 5 E S P E C I F I C A T I ON TABLE OF CONTENTS 1. PURPOSE 2 . TOKO PART NUMBER 3. APPLICATIONS 4 . STRUCTURE 5 . PACKAGE OUTLINE 6. PIN LAYOUT SIG N ATU RE DATE 7 . PACKAGE OUTLINE DIM ENSIONS/ Drawn By MARKING 8. ABSOLUTE MAXIMUM RATINGS 9. ELECTRICAL CHARACTERISTICS

1734290-2

Contextual Info: D DIM D+0.36 c 7.00 0.20 16.30 RECOMMENDED PCB LAYOUT • B - NOTES: 1. MATERIAL: HOUSING : THERMOPLASTIC HIGH TEMP., UL94V-0, COLOR: BLACK CONTACT : BRASS, THICKNESS=0.25mm. SHELL : PHOSPHOR BRONZE, THECKNESS=0.40m m. 2. FINISH : CONTACT : 3 0 u ” MIN. GOLD PLATED ON CONTACT AREA,

54AC11181

Abstract: TI018
Contextual Info: 54AC11181, 74AC11181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS T I0184— D 3119, APRIL 1989— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11181 . . . JT PACKAGE 74AC11181 . . . DW OR NT PACKAGE TOP VIEW Minimize High-Speed Switching Noise

Contextual Info: 54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES TI0053— D 2957, JUNE 1987— REVISED JANUARY 1990 • Inputs are TTL-Voltage Compatible 54ACT11020 . . . J PACKAGE 74ACT11020 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout

TI009

Contextual Info: 54AC11643, 74AC 11643 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS T I0095— D2957, JU LY 1987— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11643 . . . JT PACKAGE 74AC11643 . . . DW OR NT PACKAGE TOP VIEW Center-Pin V c c and GND Configurations to

D2957

Abstract: 1987-REVISEDAPRIL
Contextual Info: 54ACT11030,74ACT11030 8-INPUT POSITIVE-NAND GATES _ D2957. MARCH 1987-REVISEDAPRIL 1993 Inputs Are TTL*Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-PIn V^c and GNO Configurations Minimize High-Speed Switching Noise EPIC Enhanced-Perlormance Implanted

74AC108

Abstract: so 54 t 74AC11066
Contextual Info: 54AC11086, 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES TI0152— D3375, N O VEM BER 1989 • Flow-Through Architecture to Optimize PCB Layout 54AC11086 . . . J PACKAGE 74AC11086 . . . D OR N PACKAGE TOP VIEW • Center-Pin Vqc and GND Configurations to

Contextual Info: 0O.92±O.O8 15.00 <> AMP LOGO i o o ♦ C D < L 02.3±O.O8 V C M m _ 2 0 0 .1 0 I— li o -H o O O» 00 I LT t I P.C.B EDGE C 12.50 3.50 o o O m o _ l CM _ l CL CL o C\j CM m RECOMMENDED PCB LAYOUT 1.00 2.80 TYP i L 1 U- 1 C\l □ 1 1 NOTE: _ _ □