LA30 PACKAGE Search Results

PC MOTHERBOARD CIRCUIT diagram gigabyte 945gzm-s2

Abstract: gigabyte ga-945gzm-s2 circuit diagram GA-945GZM-S2 SMD transistor LD3 transistor ld12 GIGABYTE 945GZM-S2 smd LD9 PXA320 SmD TRANSISTOR a41 B38 diode smd
Contextual Info: ISP1763A PCI evaluation board UM0865 User manual Abstract This document describes board level operations of the ISP1763A PCI evaluation board. Two version of the board are available: one for the TFBGA package and the other for the VFQFPN package. The ISP1763A PCI evaluation board allows engineers and software developers to create

I960JX v363epc

Abstract: 160-Pin Flat Package pci bridge V380SDC
Contextual Info: V363EPC Data Sheet • • • • • • V363EPC Local Bus to PCI Bridge for Embedded Processors Device Highlights • Direct interface to these processors: • Up to 50 MHz on both PCI and local bus clocks • 3.3 V operation; 5 V tolerant input • Industrial temperature range

V363EPC-50LP

Abstract: V380SDC LA5-80V102MS21 B LA18 code I960JX I960JX v363epc LAD12
Contextual Info: V363EPC Data Sheet • • • • • • V363EPC Local Bus to PCI Bridge for Embedded Processors Device Highlights • Direct interface to these processors: • Up to 50 MHz on both PCI and local bus clocks • 3.3 V operation; 5 V tolerant input • Industrial temperature range

V380SDC

Abstract: ibm rev 3.3 pinouts LAD11 V3 Semiconductor V360EPC DS-EC301-0101 LAD-22 V363EPC AD30 V350EPC
Contextual Info: V363EPC A0 Data Sheet V363EPC A0 Local Bus to PCI Bridge for Embedded Processors 1.0 About the V363EPC ▼ I2O-Ready ATU and messaging unit, including hardware controlled circular queues ▼ Direct interface to these processors: • AMD AM29030/40™

VMEbus Handbook

Abstract: VMEbus interface handbook FCT245 VAC068 VAC068A VIC068A VME ACFAIL LD3011 LA-10 LD31
Contextual Info: VAC068A VMEbus Address Controller — Supports unaligned transfers Features • Optional companion part to VIC068A • Implements master/slave VMEbus interface in conjunction with the VIC068A • Complete VMEbus and I/O DMA capability for a 32-bit CPU • Complete local and VMEbus memory map decoding

VMEbus interface handbook

Abstract: transistors BC 543 Cypress VMEbus Interface Handbook diode 68A VAC068 VIC068A LA18 14 pin ld18 transistor BC 147 FCT245
Contextual Info: fax id: 5600 1V AC0 68A VAC068A VMEbus Address Controller Features — Supports unaligned transfers • Optional companion part to VIC068A • Implements master/slave VMEbus interface in conjunction with the VIC068A • Complete VMEbus and I/O DMA capability for a 32-bit

PI011

Contextual Info: . VAC068A mmàà^SSSSSSSSrnfi * .ài*' /*? / c VMEbus Address Controller • Dual UART channels on board — Double-buffered on transmit, quint-buffered on receive — Baud rate programmable • Miscellaneous features — Pin grid array or quad flatpack

VME ACFAIL

Abstract: FCT245 VIC068A CERAMIC PIN GRID ARRAY 120 pins VIC068A user guide VAC068 VAC068A LD18 LA18 code LD31
Contextual Info: VAC068A VMEbus Address Controller D Features D D Dual UART channels on board Ċ DoubleĆbuffered on transmit, quintĆbuffered on receive Optional companion part to VIC068A Implements master/slave VMEbus interface in conjunction with the VIC068A Ċ Baud rate programmable

ld18 st

Abstract: VME ACFAIL cypress VMEbus Interface handbook dio ld26
Contextual Info: fax id: 5600 VAC068A VMEbus Address Controller — Supports unaligned transfers Featu res • Optional companion part to VIC068A • Implements master/slave VMEbus interface in conjunc­ tion with the VIC068A • Complete VMEbus and I/O DMA capability for a 32-bit

VIC068A

Abstract: VAC068 VAC068A FCT245 106240 ld18 LD31 LBR 84 VMEbus interface handbook
Contextual Info: VAC068A VMEbus Address Controller Features — Supports unaligned transfers • Optional companion part to VIC068A • Implements master/slave VMEbus interface in conjunction with the VIC068A • Complete VMEbus and I/O DMA capability for a 32-bit CPU • Complete local and VMEbus memory map decoding

marking 33 micrel sot

Abstract: LA33 LA50 LA30 package tiny smps
Contextual Info: MIC5203 50mA Low-Dropout Voltage Regulator Summary Information* General Description Features The MIC5203 is a family of efficient linear voltage regulators with very low dropout voltage typically 50mV at light loads and 300mV at 50mA , and very low ground current (750pA at

LK36

Abstract: lk50 LA50 marking transistor LK-47
Contextual Info: MIC5203 Micrel, Inc. MIC5203 µCap 80mA Low-Dropout Regulator General Description Features The MIC5203 is a µCap 80mA linear voltage regulator with very low dropout voltage typically 20mV at light loads and 300mV at 80mA and very low ground current (225µA at

marking code AC sot 23-5

Abstract: lk50 4.OUT 2.GND 3.en SOT-23-5 MIC5203-3 LA36 MIC5203 LA36 diode LA30 sot-23-5 marking code marking 16 sot143
Contextual Info: MIC5203 Micrel, Inc. MIC5203 µCap 80mA Low-Dropout Regulator General Description Features The MIC5203 is a µCap 80mA linear voltage regulator with very low dropout voltage typically 20mV at light loads and 300mV at 80mA and very low ground current (225µA at

lk50

Abstract: LA50 marking transistor MIC5203 LA36 diode LA30 MIC5203-3 LA33 LA36 voltage la28 11190
Contextual Info: MIC5203 Cap 80mA Low-Dropout Regulator General Description Features The MIC5203 is a µCap 80mA linear voltage regulator with very low dropout voltage typically 20mV at light loads and 300mV at 80mA and very low ground current (225µA at 20mA output), offering better than 3% initial accuracy with

cx2812

Abstract: CX-2812 CX171 CX174 LA3122 CX87 CX134 cx59 st7033 cx109
Contextual Info: A B C D E XREF=2/3E ADDR3 XREF=2/3E ADDR2 LAD[31:0] XREF=2/1D,9/1E,12/1E XREF=13/3A,15/1C MASTERCLK AD2 105 AD3 114 AD4 AD5 CPU_ACK_N XREF=2/1A,13/2E 93 CPU_BERR_N XREF=2/1A,13/2E 100 CPU_RETRY_N XREF=2/2A,14/2A 101 ACK AD6 BUSERR AD7 RETRY AD8 AD9 AD10 CPU_BREQ_N

Contextual Info: VAC068A s s CYPRESS SEMICONDUCTOR Features • Optional companion part to VIC068A • Implements master/slave VMEbus in­ terface in conjunction with the VIC068A • Complete VMEbus and I/O DMA ca­ pability for a 32-bit CPU • Complete local and VMEbus memory

SMJ320C30

Abstract: SMJ320C40
Contextual Info: SMJ320C40 DIGITAL SIGNAL PROCESSOR SGUS017A – OCTOBER 1993 – REVISED MAY 1996 D D D D D D D D D D D D – 55°C to 125°C Operating Temperature Range; QML Processing Highest Performance Floating-Point Digital Signal Processor DSP – ’C40-50: 40-ns Instruction Cycle Time:

VIC068A

Abstract: L01B LA18 14 pin ID12 VAC068A CERAMIC PIN GRID ARRAY 120 pins CQ 817 LD207
Contextual Info: VAC068A CYPRESS VMEbus Address Controller Features • Optional companion part to VIC068A • Implements m aster/slave VMEbus interface in conjunction with the VIC068A • Complete VM Ebus and I/O DMA capability for a 32-bit CPU • Complete local and VMEbus memory

Contextual Info: SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS SGUS017H – OCTOBER 1993 – REVISED OCTOBER 2001 D D D D D D D D D D D D D SMJ: QML Processing to MIL–PRF–38535 SM: Standard Processing TMP: Commercial Level Processing TAB Operating Temperature Ranges:

ld18 st

Contextual Info: SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001 D D D D D D D D D D D D D SMJ: QML Processing to MIL−PRF−38535 SM: Standard Processing TMP: Commercial Level Processing TAB Operating Temperature Ranges:

ld18 st

Abstract: SMJ320C30 SMJ320C40 TMP320C40
Contextual Info: SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS SGUS017F – OCTOBER 1993 – REVISED APRIL 2000 D D D D D D D D D D D D D SMJ: QML Processing to MIL–PRF–38535 SM: Standard Processing TMP: Commercial Level Processing TAB Operating Temperature Ranges: – Military M –55°C to 125°C

ld18 st

Abstract: SMJ320C30 SMJ320C40 TMP320C40
Contextual Info: SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS SGUS017G – OCTOBER 1993 – REVISED JUNEL 2000 D D D D D D D D D D D D D SMJ: QML Processing to MIL–PRF–38535 SM: Standard Processing TMP: Commercial Level Processing TAB Operating Temperature Ranges: – Military M – 55°C to 125°C

Contextual Info: SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001 D D D D D D D D D D D D D SMJ: QML Processing to MIL−PRF−38535 SM: Standard Processing TMP: Commercial Level Processing TAB Operating Temperature Ranges:

SMJ320C30

Abstract: SMJ320C40 TMP320C40 socket am2 tmp pin IEEE-745 AM32
Contextual Info: SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS SGUS017B – OCTOBER 1993 – REVISED MARCH 1998 D D D D D D D D D D D D D SMJ: QML Processing to MIL–PRF–38535 SM: Standard Processing TMP: Commercial Level Processing TAB Operating Temperature Ranges: – Military M – 55°C to 125°C