JEDEC CP 20 Search Results

JEDEC Code

Abstract: JEDEC max1918 package outline weight EIAJ 133-AA JEDEC CP 28 MO133A
Contextual Info: Package Outline Dimensions 24 16.90 17.27 Max 19 18 î n r - in 13 n n n r - ii- in 6 7 0.74 12 Hitachi code JEDEC code EIAJ code Weight g CP-24DB MO-077AA SC-632-A 0.80 9.40 ± 0.25 Hitachi code JEDEC code EIAJ code Weight (g) CP-28DA MO-061 AA SC-637-B

Am29C82

Contextual Info: Am29C821 / Am29C823 Am29C921 /Am29C923 High-Performance CMOS Bus Interface Registers High-speed parallel positive edge-triggered registers with D-type flip-flops - CP-Y propagation delay = 8 ns typical • Low standby power • JEDEC FCT-compatible specs •

Am29CB21

Abstract: am29c800 cis 11-pin Am29C821
Contextual Info: Am29C821 / Am29C823 Am29C921 / Am29C923 High-Performance CMOS Bus Interface Registers • • • High-speed parallel positive edge-triggered registers with D-type flip-flops - CP-Y propagation delay - 8 ns typical Low standby power JEDEC FCT-compatible specs

SN54AHCT128

Contextual Info: SN54AHCT126, SN74AHCT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS265B - DECEMBER 1995 - REVISED JULY 1996 Inputs Are TTL-Voitage Compatible CP/C Enhanced-Performance Implanted CMOS Process High Latch-Up Immunity Exceeds 250 mA Per JEDEC Standard JESD-17

Contextual Info: SN54AHC04, SN74AHC04 HEX INVERTERS SCLS231C - OCTOBER 1995 - REVISED MARCH 1996 • • • • Operating Range 2-V to 5.5-V V jC CP/C (Enhanced-Performance Implanted CMOS Process High Latch-Up Immunity Exceeds 250 mA Per JEDEC Standard JESD-17 ESD Protection Exceeds 2000 V Per

Contextual Info: SN54AHC00, SN74AHC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES S C LS 227A -OCTOBER 1995 - REVISED MARCH 1996 Operating Range 2-V to 5.5-V Vcc CP/C Enhanced-Performance Implanted CMOS Proceas High Latch-Up Immunity Exceeds 250 mA Per JEDEC Standard JESD-17

Contextual Info: cP ÏITSU May 1997 Revision 1.0 SDC4UV7282C- 67/84/100/125 T-S 32MByte (4M x 72) CMOS Synchronous DRAM Module - ECC General Description The SDC4UV7282C-(67/84/100/125)T-S is a high performance, 32-megabtye synchronous, dynamic RAM module organized as 4M words by 72 bits, in a 168-pin, JEDEC ECC configuration, dual-in-line memory module (DIMM) package.

74AC377

Abstract: 74AC377MTC 74AC377MTCX 74AC377PC 74AC377SC 74AC377SJ 74ACT377 74ACT377SC 74ACT377 FAIRCHILD
Contextual Info: Revised March 2005 74AC377 • 74ACT377 Octal D-Type Flip-Flop with Clock Enable General Description Features The AC/ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP input loads all flip-flops simultaneously,

74AC374

Abstract: 74AC374MTC 74AC374PC 74AC374SC 74AC374SCX 74AC374SJ 74ACT374 74ACT374SC ACT374
Contextual Info: Revised March 2005 74AC374 • 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The AC/ACT374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock CP and Output Enable (OE) are common to

Contextual Info: Revised September 2003 74AC161 • 74ACT161 Synchronous Presettable Binary Counter General Description Features The AC/ACT161 are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types

74F676

Abstract: 74F676PC 74F676SC 74F676SPC M24B MS-001 MS-011 MS-013 N24A N24C
Contextual Info: Revised October 2000 74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register General Description Features The 74F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output. When the Mode M input is HIGH, information present on the

Contextual Info: Revised October 2000 74AC399 • 74ACT399 Quad 2-Port Register General Description Features The AC/ACT399 is the logical equivalent of a quad 2-input multiplexer feeding into four edge-triggered flip-flops. A common Select input determines which of the two 4-bit

Contextual Info: Revised October 2000 74AC174 • 74ACT174 Hex D-Type Flip-Flop with Master Reset General Description Features The AC/ACT174 is a high-speed hex D-type flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to

74AC574

Abstract: 74AC574MTC 74AC574PC 74AC574SC 74AC574SJ 74ACT574 74ACT574SC ACT574
Contextual Info: Revised March 2005 74AC574 • 74ACT574 Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The AC/ACT574 is a high-speed, low power octal flip-flop with a buffered common Clock CP and a buffered common Output Enable (OE). The information presented to the

74HC163

Abstract: 74VHC163 VHC163 74VHC163M 74VHC163MTC 74VHC163N 74VHC163SJ M16A M16D MTC16
Contextual Info: Revised August 2001 74VHC163 4-Bit Binary Counter with Synchronous Clear General Description The VHC163 is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation.

74VHC161

Abstract: 74hc161 application notes 74HC161 74VHC161M 74VHC161MTC 74VHC161N 74VHC161SJ M16A M16D MTC16
Contextual Info: Revised August 2001 74VHC161 4-Bit Binary Counter with Asynchronous Clear General Description Features The VHC161 is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar

DM74LS377

Abstract: DM74LS377N DM74LS377WM MS-001 MS-013
Contextual Info: Revised March 2000 DM74LS377 Octal D-Type Flip-Flop with Common Enable and Clock General Description Features The DM74LS377 is an 8-bit register built using advanced low power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a

Contextual Info: Revised September 2000 74ACT825 8-Bit D-Type Flip-Flop General Description Features The ACT825 is an 8-bit buffered register. They have Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming systems. Also included are multiple enables that allow multiuse control of the interface. The ACT825 has noninverting

LVTH273

Abstract: 74LVTH273 74LVTH273MTC 74LVTH273MTCX 74LVTH273SJ 74LVTH273WM M20D MS-013 MTC20 MAR64
Contextual Info: Revised March 2005 74LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear General Description Features The LVTH273 is a high-speed, low-power positive-edgetriggered octal D-type flip-flop featuring separate D-type inputs for each flip-flop. A buffered Clock CP and Clear

DM74LS574

Abstract: DM74LS574N DM74LS374 DM74LS574WM MS-001 MS-013
Contextual Info: Revised March 2000 DM74LS574 Octal D-Type Flip-Flop with 3-STATE Outputs General Description The DM74LS574 is a high speed low power octal flip-flop with a buffered common Clock CP and a buffered common Output Enable (OE). The information presented to the

74ABT374

Abstract: 74ABT374CMSA 74ABT374CMTC 74ABT374CPC 74ABT374CSC 74ABT374CSCX 74ABT374CSJ M20D
Contextual Info: Revised March 2005 74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The ABT374 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock CP and Output Enable (OE) are common to all flip-flops.

74F779

Abstract: 74F779PC 74F779SC M16B MS-001 MS-013 N16E
Contextual Info: Revised March 2000 74F779 8-Bit Bidirectional Binary Counter with 3-STATE Outputs General Description Features The 74F779 is a fully synchronous 8-stage up/down counter with multiplexed 3-STATE I/O ports for bus-oriented applications. All control functions hold, count up,

Contextual Info: HARRIS SEIUCOND SECTOR 37E D • 430E271 0025543 3 « H A S ’_ CD54/74AC299, CD54/74AC323 CD54/74ACT299, CD54/74ACT323 Advance Information S O - 1 20 — Ô Ë 1 - 2 19 - S I ÖC2 - 3 16 - 0 S 7 vcc | / 06 —

100329PC

Abstract: 100329QC 100329QI MO-047 N24E V28A
Contextual Info: Revised August 2000 100329 Low Power Octal ECL/TTL Bidirectional Translator with Register General Description Features The 100329 is an octal registered bidirectional translator designed to convert TTL logic levels to 100K ECL logic levels and vice versa. The direction of the translation is determined by the DIR input. A LOW on the output enable input