SCLS265B Search Results

SN54AHCT128

Contextual Info: SN54AHCT126, SN74AHCT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS265B - DECEMBER 1995 - REVISED JULY 1996 Inputs Are TTL-Voitage Compatible CP/C Enhanced-Performance Implanted CMOS Process High Latch-Up Immunity Exceeds 250 mA Per JEDEC Standard JESD-17

SN74ALVCH162245

Abstract: Schottky Barrier Diode Bus-Termination Array SN7400 CLOCKED SLLS210 SCAD001D TEXAS INSTRUMENTS SN7400 SERIES buffer SN74LVCC4245 sn74154 SDAD001C SN7497
Contextual Info: Section 4 Logic Selection Guide ABT – Advanced BiCMOS Technology . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 ABTE/ETL – Advanced BiCMOS Technology/ Enhanced Transceiver Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9

Contextual Info: SN54AHC74, SN74AHC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCLS265B- DECEMBER 1995- REVISED JULY 1696 Operating Range 2-V to 5.5-V Mq c EPIC Enhanced-Performance Implanted CMOS Process