SN74AHC74 Search Results

Contextual Info: SN54AHC74, SN74AHC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCLS255E – DECEMBER 1995 – REVISED NOVEMBER 1998 D D D SN54AHC74 . . . J OR W PACKAGE SN74AHC74 . . . D, DB, DGV, N, OR PW PACKAGE TOP VIEW Operating Range 2-V to 5.5-V VCC

Contextual Info: SN74AHC74-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCLS489 – JUNE 2003 D D D D D D D D D D OR PW PACKAGE TOP VIEW Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C

A115-A

Abstract: C101 SN54AHC74 SN74AHC74
Contextual Info: SN54AHC74, SN74AHC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCLS255J – DECEMBER 1995 – REVISED JULY 2003 D Operating Range 2-V to 5.5-V VCC Latch-Up Performance Exceeds 250 mA Per JESD 17 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D

SN74AHC74MPWREP

Abstract: SN74AHC74 SN74AHC74MDREP ahc74ep
Contextual Info: SN74AHC74-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCLS489 – JUNE 2003 D D D D D D D D D D OR PW PACKAGE TOP VIEW Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C

Contextual Info: SN54AHC74, SN74AHC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCLS255J – DECEMBER 1995 – REVISED JULY 2003 D Operating Range 2-V to 5.5-V VCC Latch-Up Performance Exceeds 250 mA Per JESD 17 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D

Contextual Info: SN74AHC74-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCLS489 – JUNE 2003 D D D D D D D D D D OR PW PACKAGE TOP VIEW Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C

Contextual Info: SN54AHC74, SN74AHC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCLS255J – DECEMBER 1995 – REVISED JULY 2003 D Operating Range 2-V to 5.5-V VCC Latch-Up Performance Exceeds 250 mA Per JESD 17 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D

Contextual Info: SN74AHC74QĆQ1 DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOP WITH CLEAR AND PRESET SGDS020A − FEBRUARY 2002 − REVISED APRIL 2008 D Qualified for Automotive Applications D EPIC Enhanced-Performance Implanted D OR PW PACKAGE (TOP VIEW CMOS) Process

Contextual Info: SN74AHC74QĆQ1 DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOP WITH CLEAR AND PRESET SGDS020A − FEBRUARY 2002 − REVISED APRIL 2008 D Qualified for Automotive Applications D EPIC Enhanced-Performance Implanted D OR PW PACKAGE (TOP VIEW CMOS) Process

Contextual Info: SN74AHC74Q-Q1 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SGDS020 – FEBRUARY 2002 D D D D D D D D OR PW PACKAGE TOP VIEW Qualification in Accordance With AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control

Contextual Info: SN74AHC74-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCLS489 – JUNE 2003 D D D D D D D D D D OR PW PACKAGE TOP VIEW Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C

Contextual Info: SN74AHC74QĆQ1 DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOP WITH CLEAR AND PRESET SGDS020A − FEBRUARY 2002 − REVISED APRIL 2008 D Qualified for Automotive Applications D EPIC Enhanced-Performance Implanted D OR PW PACKAGE (TOP VIEW CMOS) Process

ha74

Contextual Info: SN54AHC74, SN74AHC74 www.ti.com SCLS255K – DECEMBER 1995 – REVISED DECEMBER 2013 Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset Check for Samples: SN54AHC74, SN74AHC74 FEATURES DESCRIPTION • • The ’AHC74 dual positive-edge-triggered devices are

Contextual Info: SN54AHC74, SN74AHC74 www.ti.com SCLS255K – DECEMBER 1995 – REVISED DECEMBER 2013 Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset Check for Samples: SN54AHC74, SN74AHC74 FEATURES DESCRIPTION • • The ’AHC74 dual positive-edge-triggered devices are

Contextual Info: SN74AHC74-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCLS489 – JUNE 2003 D D D D D D D D D D OR PW PACKAGE TOP VIEW Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C

SN74AHC74

Abstract: SN74AHC74MDREP SN74AHC74MPWREP
Contextual Info: SN74AHC74-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCLS489 – JUNE 2003 D D D D D D D D D D OR PW PACKAGE TOP VIEW Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C

ha74

Abstract: A115-A C101 SN54AHC74 SN74AHC74
Contextual Info: SN54AHC74, SN74AHC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCLS255H – DECEMBER 1995 – REVISED MARCH 2002 D D D SN54AHC74 . . . J OR W PACKAGE SN74AHC74 . . . D, DB, DGV, N, NS, OR PW PACKAGE TOP VIEW Operating Range 2-V to 5.5-V VCC

SN74AHC74RGYR

Abstract: SN54AHC74 SN74AHC74 A115-A C101
Contextual Info: SN54AHC74, SN74AHC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCLS255J – DECEMBER 1995 – REVISED JULY 2003 D Operating Range 2-V to 5.5-V VCC Latch-Up Performance Exceeds 250 mA Per JESD 17 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D

Contextual Info: SN54AHC74, SN74AHC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCLS255J – DECEMBER 1995 – REVISED JULY 2003 D Operating Range 2-V to 5.5-V VCC Latch-Up Performance Exceeds 250 mA Per JESD 17 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D

Contextual Info: SN74AHC74-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCLS489 – JUNE 2003 D D D D D D D D D D OR PW PACKAGE TOP VIEW Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C

Contextual Info: SN74AHC74-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCLS489 – JUNE 2003 D D D D D D D D D D OR PW PACKAGE TOP VIEW Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C

SN74AHC74DR

Abstract: SN74AHC74PWR
Contextual Info: SN54AHC74, SN74AHC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCLS255J – DECEMBER 1995 – REVISED JULY 2003 D Operating Range 2-V to 5.5-V VCC Latch-Up Performance Exceeds 250 mA Per JESD 17 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D

SN74AHC74MPWREP

Abstract: SN74AHC74 SN74AHC74MDREP
Contextual Info: SN74AHC74-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCLS489 – JUNE 2003 D D D D D D D D D D OR PW PACKAGE TOP VIEW Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C

SN74AHC74Q

Abstract: SN74AHC74QDRG4Q1 SN74AHC74QDRQ1 SN74AHC74QPWRG4Q1 SN74AHC74QPWRQ1
Contextual Info: SN74AHC74QĆQ1 DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOP WITH CLEAR AND PRESET SGDS020A − FEBRUARY 2002 − REVISED APRIL 2008 D Qualified for Automotive Applications D EPIC Enhanced-Performance Implanted D OR PW PACKAGE (TOP VIEW CMOS) Process