J3 IC Search Results

DB3 C118

Abstract: db3 c113 DB3 C144 LED_RED 103308-1 DB3 c112 CC2420 J2-17 M30280F J416
Contextual Info: 5 4 3 C20 0.22uF 2 1 DVDD_5.0V Power Source Select U6 FoUSB_PWR 5 C18 6 C19 2.2uF + REG711-5.0 C15 0.01uF D5 R14 CC_CS CC_CLK CC_MISO CC_MOSI 4 BYPASS GND 2 LDO_OUT J3-3 J3-2 J3-1 J2-20 J2-11 J2-10 J2-9 J2-8 LP2992AIM5-3.3 680 ICD_BUSY ICD_CLK ICD_IN ICD_OUT

Contextual Info: LDWER ROW ELECTRICAL SPECIFICATIONS: 1.0 TURNS RATID P1-P2-P3 i (J1 -J2 ) (P 4 -P 5 -P 6 ) i C J3 -J6 ) 2.0 INDUCTANCE CP6-P4) (P3-P1) 3.0 LEAKAGE INDUCTANCE P6-P4 (WITH J6 AND J3 SHORT) P3-P1 (WITH J2 AND J1 SHORT) 4.0 INTERVINDING CAPACITANCE <P6,P5,P4) TO <J6 ,J3 )

Contextual Info: LDVER RDW ELECTRICAL SPECIFICATIONS* l.D TURNS RATIO P 1-P E-P3 i (J1 -J2 ) CP 4-P 5 -P 6) ; (J3 -J6 > 2.0 INDUCTANCE <P6-P4> (P3-PL) 3.0 LEAKAGE INDUCTANCE P 6 -P 4 (WITH J6 AND J3 SHDRT) P3-P1 (WITH J2 AND JL SHDRT) 4.0 INTERW INDING CAPACITANCE CP6.P5.P4) TD (J6,J3)

30089

Contextual Info: LDWER RDW ELECTRICAL SPECIFICATIONS« 1.0 TURNS RATID P1-P2-P3 i (J 1 -J2 ) (P 4 -P 5 -P 6 ) i C J3 -J6 ) 2.0 INDUCTANCE <P6-P4> (P3-P1) 3.0 LEAKAGE INDUCTANCE P 6-P4 (WITH J6 AND J3 SHORT) P3-P1 (WITH J2 AND J1 SHDRT) 4.0 INTERWINDING CAPACITANCE <P6,P5,P4) TD < J6,J3)

C1384

Abstract: C1143
Contextual Info: ELECTRICAL SPECIFICATIONS 1.0 TURNS RATIO P 6 -P 8 -P 3 i ( J 6 - J 3 ) (P2 -P 7 -P 1 ) i (J2 -J1 ) 2.0 INDUCTANCE <P6-P3)=<J6-J3) (P2-P1) 3.0 LEAKAGE INDUCTANCE P 6 -P 3 (WITH J6 AND J3 SHDRT) P2-P1 (WITH J2 AND J1 SHDRT) 4.0 INTERWINDING CAPACITANCE <P6,P3) TD <J6,J3>

50MHZ

Contextual Info: S c h e m a t ic : E le c t r ic a l Isolation Voltage: S p e c if ic a t io n s : 1500Vac J1.J2 to (P1.P3) Isolation Voltage: 1500Vac (J3.J6) to (P4.P6) Turns Ratio: (PB-P5-F4):{J6-J3)=1,41 CT:1 CT±3% Turns Ratio: (P3-P2-P1):(J2-J1)=1CT:1CT±3% OCL: J3 -J6 : 350uH Min @100KHz 1D0mV SmADC

TE28F640J3C-120

Abstract: 28F64J3 28f256j3c SL894 RC28F128J3C-150 SL897 28F128j3c TE28F640J3C120 sl896 28F320J3C
Contextual Info: Intel StrataFlash Memory J3 256-Mbit J3 Family Specification Update June 2005 The 28F256J3, 28F128J3, 28F640J3, and 28F320J3 may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current

DP5Z1MM8NKH3

Abstract: 00FIH
Contextual Info: 1Mx8, 120 - 200ns, STACK/PGA 30A189-01 A 8 Megabit FLASH EEPROM DP5Z1MM8NKY/I3/H3/J3/DP5Z1MX8NKA3 PRELIMINARY DESCRIPTION: The DP5Z1MM8NKY/I3/H3/J3/DP5Z1MX8NKA3 ‘’SLCC’’ devices are a revolutionary new memory subsystem using Dense-Pac Microsystems’

DP5Z1MM16PH3

Abstract: DP5Z1MM16PI3 DP5Z1MM16PJ3 DP5Z1MM16PY DP5Z1MW16PA3
Contextual Info: 1Mx16, 120 - 200ns, STACK/PGA 30A162-21 A 16 Megabit FLASH EEPROM DP5Z1MM16PY/I3/H3/J3/DP5Z1MW16PA3 PRELIMINARY DESCRIPTION: The DP5Z1MM16PY/I3/H3/J3/DP5Z1MW16PA3 ‘’SLCC’’ devices are a revolutionary new memory subsystem using Dense-Pac Microsystems’

Contextual Info: LOWER ROW ELECTRICAL SPECIFICATIONS: OPERATING TEMPERATURE RANGE: 1.0 TURNS RATIO: P1 - P2 - P 3 : (J1 - J2 ) (P4 - P5 - P 6 ) : (J3 - J6 ) 2.0 INDUCTANCE: 3.0 LEAKAGE INDUCTANCE: 4.0 INTERWINDING CAPACITANCE: (P6,P5,P4) TO (J6 ,J3 ) (P3,P2,P1) TO (J2 ,J1 )

1117 S Transistor

Abstract: TOSHIBA bat Transistor b 1117
Contextual Info: TOSHIBA TENTATIVE GT5J311,GT5J311 SM TOSHIBA INSULATED GATE BIPOLAR TRANSISTOR G T5 J3 1 1 , SILICON N CHANNEL IGBT G T 5 J3 1 1 (S M ) Unit in mm HIGH POWER SWITCHING APPLICATIONS GT5J311 MOTOR CONTROL APPLICATIONS 10.3 MAX The 3rd Generation Enhancement-Mode

GT10J312

Abstract: CP20A
Contextual Info: GT10J312,GT10J312 SM TOSHIBA TOSHIBA INSULATED GATE BIPOLAR TRANSISTOR SILICON N CHANNEL IGBT G T 1 0 J3 1 2 , G T 1 0 J3 1 2 ( S M ) Unit in mm HIGH POWER SWITCHING APPLICATIONS GT10J312 MOTOR CONTROL APPLICATIONS 1.32 The 3rd Generation Enhancement-Mode

600-8-2

Abstract: IT220
Contextual Info: lOOOpFj 2 K V ELECTRICAL SPECIFICATIONS: 1.0 TURNS RATIO: P6 - P5 - P4 : (J6 - J3 ) (P3 - P2 -P1 ) : (J2 - J1 ) 1CT : 1CT± 3% 1CT : 1CT ± 3% 2.0 INDUCTANCE: 350uH MIN. @ 0.1V, 350uH MIN. @ 0.1V, 3.0 (P6 -P4 ) (P3 -P1 ) LEAKAGE INDUCTANCE: P6-P4 (WITH J6 AND J3 SHORT)

CD075014 2X5

Abstract: CD075014 ATTiny23V PL-326 atmel 0409 680R MBR0520L NC7SZ57P6X STK600 C4022
Contextual Info: 5 4 3 2 1 J1 and J2 goes down to the mother board. ATTiny23U / ATTiny43U Routing&Socket card SILK: USAGE: BOOST regulator: open Vtarget jumper on mainboard short J8 strap wire from mainboard Vtarget pin1 to J3 Vbat pin 1 w/o BOOST regulator short J3 (Vbat)

Magjack Bel Stewart RJ45

Contextual Info: 1CT:1CT 75 Iji ~lauuuJ~ js m m _ |J2 |J3 1CT:1CT © |J4 |J5 P6 |J6 75 |J7 75 IJ8 1000pF, 2KV SHIELD NDTES 1,0 P IN S WITHGUT EL E C T R IC A L CDNNECTIDN ARE DMITTED, ELECTRICAL SPECIFICATIONS: 1.0 TURNS RATIO: P 3 - P 5 - P 6 : (J3 -J6 ) ( P 1 - P 3 - P 2 ) : (J1 -J2 )

CDS0892

Abstract: QQ-S-571 SN63
Contextual Info: F E AT U R E S MODEL NO. CDS0892 1550 - 1850 MHz 4 dB Gain Non-Reflective TTL Driver Replaceable SMA Connectors HDI Connectorized SP2T w/Amp 1.00 ±.03 PART IDENTIFICATION .104 X .304 SLOT THRU TYP J3 .25 J1 SWITCH SP2T J2 .750 J1 J3 AMPLIFIER J2 +15V CONT

IC24011-0101T

Contextual Info: ELECTRICAL SPECIFICATIONS 25JC unless otherwise noted: 350uH min., 100kHz, lOOmV, 8mADC, J1-J2; J3-J6, Lp. 1500Vrms for 1 minute between P l-Jl tie P1+P4 . (P1-P3):(J1-J2) = 1:1, ± 2%. (P4-P6):(J3-J6) = 1:1, ± 2%. INSERTION LOSS: -l.OdB max., 1MHz - 100MHz.

MAGJACK rj45 connector

Contextual Info: 1CT i 1CT J1 J2 J3 J4 J5 J6 J7 J8 TX+ TXRX+ RX- lOOOpF, 2 K V NDTES ELECTRICAL SPECIFICATIONS: 1,0 P IN S WITHDUT EL E C T R IC A L CDNNECTIDN ARE □MITTED, 1.0 TURNS RATIO: P 4 - P 5 - P 6 : (J3 -J6 ) ( P 3 - P 2 - P 1 ) : (J1 -J2 ) 1CT : 1CT± 3% 1CT : 1CT ± 3%

Contextual Info: F E AT U R E S MODEL NO. CAM09120 430 - 470 MHz Power Out +64 dBM Gain 21 dB Efficiently 57% Duty Cycle 15% J1 Ou tlin e HPA PART IDENTIFICATION .83 (J2) (J3) PEAK DET PHASE ADJ 5.06 J2 OUTPUT AMP J1 INPUT 3.44 2.54 2.20 1.03 1.00 J3 SIGNAL 2X 4.50 1.14

1230A1

Contextual Info: 16 Megabit FLASH EEPROM D E N S E - P A C M I C K OS V S T M S \í DP5Z1MM16PY/I3/H3/J3/DP5Z1MW16PA3 AD VAN CED IN FO RM ATIO N DESCRIPTION: The DP5Z1MM16PY/Í3/H3/J3/DP5Z1MW16PA3 "SLCC" devices are a revolutionary new memory subsystem using Dense-Pac Microsystems'

SI-30005

Contextual Info: LDWER ROW ELECTRICAL SPECIFICATIONS« 1.0 TURNS RATID P1-P2-P3 i (J1-J2) (P 4 -P 5 -P 6 ) i CJ3-J6) 2.0 INDUCTANCE (P6-P4) (P3-P1) 3.0 LEAKAGE INDUCTANCE P6-P4 (WITH J6 AND J3 SHORT) P3-P1 (WITH J2 AND J1 SHDRT) 4.0 INTERWINDING CAPACITANCE <P6,P5,P4) TD <J6,J3)

j1 3003

Contextual Info: 10 0 0 p F 1 2 K V ELECTRICAL SPECIFICATIONS: NDTES 1.0 TURNS RATIO: P 6 - P 5 - P 4 (P 3- P 2- P 1 : (J6- J3 : (J2- J1) 2.0 INDUCTANCE: 3.0 LEAKAGE INDUCTANCE: 4.0 INTERWINDING CAPACITANCE: 5.0 DC RESISTANCE: (J6 - J3 )= (J2 - J1 ) (P 6 - P 4 ) (P 3 - P 1 )

TMS34061FNL

Abstract: lad1-5v TMS34070NL S3406 TL 413 SPVU001 MJ340 TA2625
Contextual Info: SM J 3 4 0 1 0 GRAPHICS SYSTEM PROCESSOR NOVEMBER 1 98 8 - • Military Temperature . . . - 5 5 ° C to 12 5°C • Instruction Cycle Time: 200 ns . . . S M J3 4010-40 160 ns . . . S M J3 4010-50 REVISED SEPTEMBER 1989 GB PACKAGE 68-PIN GRID ARRAY TOP VIEW

Contextual Info: 1CT : 1CT J1 TX+ J2 TX- J3 RX+ J4 J5 J6 RX- J7 J8 lOOOpF, 2 K V ELECTRICAL SPECIFICATIONS: NDTES 1.0 TURNS RATIO: P 4 - P 5 - P 6 : (J3 -J6 ) ( P 3 - P 2 - P 1 ) : (J1 -J2 ) 1CT : 1CT± 3% 1CT : 1CT ± 3% 1,0 PINS WITHDUT ELECTRICAL CONNECTION ARE OMITTED,