IR TK 69 Search Results

IC CD 4049

Abstract: 7561A STK6982
Contextual Info: SAN Y O S E M I C O N D U C T O R CORP 7b D[f| STK6972C DDDnflM □ M ~ D T -fgc/J-¡3 C IR C U IT D R A W I N G N O .B D 4 9 t h ic k film h y b r id 1C DC MOTOR DRIVER [2-CHANNELS 4054 Use • DC m otor fo r V T R , CD, etc. Features ■ Linear operation, bidirectional drive control

836BH-0268

Abstract: TSS0P16 TK14588 TK14 TK14584M TK14588V TSS0P-16 AMMS
Contextual Info: T K 1 4 5 8 4 M / / TK14588V T K 1 4 5 8 4 M /T K 1 4 5 8 8 V / J T A JjMÎ&m tëW±9bfè K 14584M : MFP12 (TK14588V : TSS0P16) ~22MHz 2.3-5.5V -lMHz m'M Vs—* =1>S<U—? (TK14588V , ~2Mbps) 'co77°y^—> 3 y ? - a 7 /v c o f e r t ^ ^ ig LSS<^3E1'^^¿á5fci9^i-(0Tr\ Jf-á ó W T * íié T é V '0

M5M4V16169TP-10

Abstract: mitsubishi scr
Contextual Info: MITSUBISHI LSIs M 5M 4V16169TP-10,-12,-15,-20 16M 1M-W0RD BY 16-BIT CACHED DRAM WITH 16K(1024-WORD BY 16-BIT)SRAM DESCRIPTION The M 5 M 4V 161 69T P is a 16M - bit Cached DRAM which integrates input registers, a 1 0 4 8 5 7 6 - w ord by 1 6 - bit dynamic m em ory array and a 1 0 2 4 - w ord by 1 6 - bit static

Contextual Info: 2 1 + * * 83 00 3 4 Series * * * Material ; * I n s u la t o r : UL 9 4 V - 0 PBT * C o n ta c t : P h o s p h o r Bronze + P la tin g : Tin p la te d 1 2 0 / / m in . o ver 3 0 ~ 5 0 y u ” nickel overall 2.540± 0.05 .lOOi.OOe ii— 3 - - ^ - - ^ —

Contextual Info: K7R323684M K7R321884M K7R320884M Preliminary 1Mx36 & 2Mx18 & 4Mx8 QDRTM II b4 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit QDRTM II b4 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. June 30, 2001 Advance 0.1 1. Package dimension modify.

Contextual Info: NOTES: D au g h tercard S o c k e t C o n n e c to rs E R EVISED PER ECR« 6900 NX6B0BA11A1AF 2. [3] |T| 5. BY A PPD DATE V.B.H. NX SERIES M e tC o n -2 TH IS CONNECTOR IS DESIGNED TO MEET THE A P P L IC A B L E PERFORMANCE REQUIREMENTS OF IEC 61076-4-101 AND BELLCORE GR-1217-CORE.

Contextual Info: IS61C632A m i 32K x 32 SYNCHRONOUS PIPELINED STATIC RAM SEPTEMBER 1997 FEATURES DESCRIPTION • The I S S I IS61C632A is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the i486 , Pentium™,

Contextual Info: TOSHIBA TC55YD1837YB-333,-250 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT 524,288-WORD BY 36-BIT SYNCHRONOUS STATIC RAM SILICON GATE CMOS SigmaRAM, 21x1 Dp DESCRIPTION The TC55YD1837YB is a 18,874,368-bit synchronous I/O common Sigma SDR static random access memory

Contextual Info: ISSI IS61SP6464 64Kx 64 SYNCHRONOUS PIPELINE STATIC RAM PRELIMINARY APRIL 1999 FEATURES DESCRIPTION • Fast access time: The IS S IIS61SP6464 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the i486 , Pentium™,

TK116XX

Contextual Info: RJTOKO _ TK116xxU ra iU H O IM ^ O T iFiODFDO^TD ^ THREE TERMINAL VOLTAGE REGULATOR FEATURES APPLICATIONS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Low Dropout Voltage Very Low Standby Current No Load

Contextual Info: DATA S H EE T_ MOS INTEGRATED CIRCUIT /¿PD464518L, 464536L 4M-BIT Bi-CMOS SYNCHRONOUS FAST STATIC RAM 256K-WORD BY 18-BIT / 128K-WORD BY 36-BIT LVTTL INTERFACE Description The ,uPD464518L is a 262,144 words by 18 bits, and the ,uPD464536L is a 131,072 words by 36 bits synchronous

CQ226

Abstract: tk 69 K7Z167285A
Contextual Info: K7Z167285A Preliminary 256Kx72 Double Late Write SigmaRAMTM Document Title 256Kx72 Double Late Write SigmaRAM TM Revision History Rev. No. 0.0 0.1 0.2 0.3 History Draft Date Remark 1. 1. 1. 1. November 2, 2000 March 30, 2001 May 16, 2001 July 18, 2001 Preliminary

Contextual Info: KM736FV4022 KM718FV4022 PRELIMINARY 128Kx36 & 256Kx18 SRAM Document Title 128Kx36 & 256Kx18 Synchronous Pipelined SRAM Revision History Rev. No. History Rev. 0.0 - Preliminary specification release Rev. 0.1 - Change specification format. No change was made in parameters.

V 7271 U

Abstract: 07280 d752
Contextual Info: PANASONIC INDL/ELEK 6932852 - C I O 7E üF|^32fl52 PANASONIC INDL*ELECTRONIC 72C LS TTL DN74LSS/U-X DOOTSTfl t> 07278 D DN74LS640/DN74LS640S DN 74LS640/DN 74LS640S Octal Bus Transceivers with 3 - state Outputs mm m DN74 L S 6 40/S l i , S t e f f i h 7 > X 5 -j ? / U y - A £ 8

SMAJ15CA xm

Contextual Info: SMAJ SERIES DATA SHEET TRANSIENT VOLTAGE SUPPRESSOR – SMAJ SERIES FEATURE — — — — — — — — — — — For surface mounted applications in order to optimize board space. Low profile package. Built-in strain relief. Glass passivated junction. Low inductance.

Contextual Info: WESTCODE An Date:- 3 Aug, 2006 Data Sheet Issue:- 2 IXYS Company Provisional Data High Power Sonic FRD Type E1500NH48P Absolute Maximum Ratings VOLTAGE RATINGS MAXIMUM LIMITS UNITS VRRM Repetitive peak reverse voltage note 1 4800 V VRSM Non-repetitive peak reverse voltage (note 1)

D78042

Contextual Info: DATA SHEET 8-BIT SINGLE-CHIP MICROCOMPUTER The ,uPD78042F, ,uPD78043F, ,uPD78044F, and ^P D 7 8 0 4 5 F are 8-bit single-chip m icrocom puters that incorpo­ rate many hardware peripherals such as an FIP controller/driver, 8-bit resolution A/D converter, timer, serial

SMAJ5.0A

Contextual Info: SMAJ SERIES DATA SHEET TRANSIENT VOLTAGE SUPPRESSOR – SMAJ SERIES FEATURE — — — — — — — — — — — For surface mounted applications in order to optimize board space. Low profile package. Built-in strain relief. Glass passivated junction. Low inductance.

Contextual Info: KM736FV4021 KM718FV4021 PRELIMINARY 128KX36 & 256KX18 SRAM 128Kx36 & 256Kx18 Synchronous Pipelined SRAM Revision History Draft Date Rem ark Rev. No. H istory Rev. 0.0 - Preliminary specification release Rev. 0.1 - Change specification format. No change was made in parameters.

MOSYS

Abstract: MC8051M36 MC8051M36L-7R5VI 1.8V SRAM
Contextual Info: ♦ MC8051M36 36-Mbit: 1Mx36 M o Sys * Symmetric Pipelined Burst SRAM • High Performance • 133-200MHz Speed grades • 3-1-1-1 Burst Read • 3-1-1-1 Burst Write • 3-1-1-1-1-1-1-1. pipelined operation lu • Symm etric Pipeline • No bus turnaround latency allowing 100% bus efficiency

TSAL6200

Abstract: temic infrared
Contextual Info: Temic Semiconductors TSAL6200 GaAs/GaAlAs IR Emitting Diode in 0 5 mm T-1% Package Description TSAL6200 is a high efficiency infrared emitting diode in GaAIAs on GaAs technology, molded in clear, bluegrey tinted plastic packages. In comparison with the standard GaAs on GaAs technol­

Contextual Info: TOSHIBA TC55YD1873YB-333,-250 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT 262,144-WORD BY 72-BIT SYNCHRONOUS STATIC RAM SILICON GATE CMOS SigmaRAM, 21x1 Dp DESCRIPTION The TC55YD1873YB is a 18,874,368-bit synchronous I/O common Sigma SDR static random access memory

Contextual Info: PRELIMINARY DATA SHEET 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The ¿¡PD780053,780054,780055,780056 and 780058 are members of the ¿¡PD780058 subseries in the 78K/0 series. These microcontrollers suppress the EMI Electro Magnetic Interference noise internally generated to the

51 ti jbr

Abstract: IS61SP6436
Contextual Info: IS61SP6436 M 64Kx 36 SYNCHRONOUS PIPELINED STATIC RAM PRELIMINARY D ecem ber 1997 FEATURES DESCRIPTION The IS S I IS61SP6436 is a high-speed, • Internal s e lf-tim e d w rite c ycle • Individua l B yte W rite C o n tro l and G lob al W rite • C lo c k co n tro lle d , re g iste re d a dd re ss, d a ta and