15MMX17MM Search Results

K7R321884M-FC25

Abstract: K7R321884M K7R321884M-FC16 K7R321884M-FC20 K7R323684M K7R323684M-FC16 K7R323684M-FC20 K7R323684M-FC25
Contextual Info: K7R323684M K7R321884M 1Mx36 & 2Mx18 QDRTM II b4 SRAM Document Title 1Mx36-bit, 2Mx18-bit QDR TM II b4 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. June 30, 2001 Advance 0.1 1. Package dimension modify. P.20 from 13mmx15mm to 15mmx17mm

K7M643635M-Q

Contextual Info: K7N643631M K7N641831M Preliminary 2Mx36 & 4Mx18 Pipelined NtRAM TM Document Title 2Mx36 & 4Mx18-Bit Pipelined NtRAMTM Revision History History Draft Date Remark 0.0 1. Initial document. Sep. 30. 2002 Advance 0.1 1. Delete the speed bins FT : 7.5ns, 8.5ns / PP : 200MHz

Contextual Info: IS61DDP2B22M18A IS61DDP2B21M36A 2Mx18, 1Mx36 36Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.0 Cycle Read Latency) FEATURES •                   1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: IS61QDP2B41M18A IS61QDP2B451236A 1Mx18 , 512Kx36 18Mb QUAD-P Burst 4 SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                    512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: IS61QDB41M18A IS61QDB451236A 1Mx18, 512Kx36 18Mb QUAD Burst 4 SYNCHRONOUS SRAM FEATURES •                   512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: IS61DDP2B21M18A IS61DDP2B251236A 1Mx18, 512Kx36 18Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.0 Cycle Read Latency) FEATURES •                   512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: IS61QDP2B41M18A/A1/A2 IS61QDP2B451236A/A1/A2 1Mx18 , 512Kx36 18Mb QUADP Burst 4 SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                     512Kx36 and 1Mx18 configuration available.

Contextual Info: K7R323684C K7R321884C K7R320984C Preliminary TM 1Mx36, 2Mx18 & 4Mx9 QDR II b4 SRAM 36Mb QDRII SRAM Specification 165 FBGA with Pb & Pb-Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

Contextual Info: K7B323625M K7B321825M 1Mx36 & 2Mx18 Synchronous SRAM Document Title 1Mx36 & 2Mx18-Bit Synchronous Burst SRAM Revision History Rev. No. 0.0 History 1. Initial draft Draft Date May. 10. 2001 Remark Advance 0.1 1. Add 165FBGA package Aug. 29. 2001 Preliminary

Contextual Info: K7N323601M K7N321801M 1Mx36 & 2Mx18 Pipelined NtRAMTM Document Title 1Mx36 & 2Mx18-Bit Pipelined NtRAMTM Revision History Rev. No. 0.0 0.1 0.2 0.3 0.4 0.5 1.0 History Draft Date Remark 1. Initial document. 1. Add 165FBGA package 1. Update JTAG scan order 2. Speed bin merge.

Contextual Info: Samsung Samsung Secret Secret SAMSUNG QDRII+/DDRII+ 16Mb C-die Specification Change Notice July, 2008 Product Planning & Application Engineering Team MEMORY DIVISION SAMSUNG ELECTRONICS Co., LTD Product Product Planning Planning & & Application Application Eng.

Contextual Info: K7N643645M K7N641845M 2Mx36 & 4Mx18 Pipelined NtRAMTM 72Mb NtRAMTM Specification 100TQFP/165FBGA with Pb/Pb-Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

IS61QDB21M18A

Contextual Info: IS61QDB21M18A IS61QDB251236A 1Mx18, 512Kx36 18Mb QUAD Burst 2 Synchronous SRAM FEATURES •                  512Kx36 and 1Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window.

IS61QDB41M18A

Contextual Info: IS61QDB41M18A IS61QDB451236A 1Mx18, 512Kx36 18Mb QUAD Burst 4 SYNCHRONOUS SRAM FEATURES •                   512Kx36 and 1Mx18 configuration available. On-chip Delay-Locked loop (DLL) for wide data valid

IS61QDB42M36A

Abstract: B0821
Contextual Info: IS61QDB44M18A IS61QDB42M36A 4Mx18, 2Mx36 72Mb QUAD Burst 4 SYNCHRONOUS SRAM FEATURES •                   2Mx36 and 4Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window.

Contextual Info: IS61QDPB42M18A/A1/A2 IS61QDPB41M36A/A1/A2 2Mx18, 1Mx36 36Mb QUADP Burst 4 SYNCHRONOUS SRAM (2.5 Cycle Read Latency) FEATURES • • • • • • • • • • • • • • • • • • • • • 1Mx36 and 2Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data

Contextual Info: IS61DDB21M18A IS61DDB251236A 1Mx18, 512Kx36 18Mb DDR-II Burst 2 CIO Synchronous SRAM FEATURES •                  512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: IS61QDP2B41M18A/A1/A2 IS61QDP2B451236A/A1/A2 1Mx18 , 512Kx36 18Mb QUAD-P Burst 4 SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                    512Kx36 and 1Mx18 configuration available.

Contextual Info: IS61DDB41M18A IS61DDB451236A 1Mx18, 512Kx36 18Mb DDR-II Burst 4 CIO Synchronous SRAM FEATURES •                  512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

IS61DDB21M36A

Contextual Info: IS61DDB22M18A IS61DDB21M36A 2Mx18, 1Mx36 36Mb DDR-II Burst 2 CIO SYNCHRONOUS SRAM FEATURES •                  1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: IS61DDP2B24M18A/A1/A2 IS61DDP2B22M36A/A1/A2 4Mx18, 2Mx36 72Mb DDR-IIP Burst 2 CIO SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                     2Mx36 and 4Mx18 configuration available.

Contextual Info: IS61DDP2B24M18A/A1/A2 IS61DDP2B22M36A/A1/A2 4Mx18, 2Mx36 72Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.0 Cycle Read Latency) FEATURES •                   2Mx36 and 4Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: IS61DDB41M18A IS61DDB451236A 1Mx18, 512Kx36 18Mb DDR-II Burst 4 CIO SYNCHRONOUS SRAM FEATURES •                  512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: IS61QDB21M18A IS61QDB251236A 1Mx18, 512Kx36 18Mb QUAD Burst 2 Synchronous SRAM FEATURES •                  512Kx36 and 1Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window.