INP12 Search Results

AA30

Abstract: AA34 AB30 M21110 PRBS MSB NCN30
Contextual Info: M21110 17 x 17 3.2 Gbps Crosspoint Switch with Input Equalization Data Sheet Features - 4 Terminal Descriptions - 5 Specification Tables - 7 Functional Description - 17 Register Information - 21 Package Information - 28 World Wide Sales Companies - 37 21110-DSH-001-B, 3/27/03

outp32

Abstract: M21130 AA30 AA34 AB30 OUTP23 NCN30
Contextual Info: M21130 68 x 68 3.2 Gbps Crosspoint Switch with Input Equalization Data Sheet Features - 4 Terminal Descriptions - 5 Specification Tables - 8 Functional Description - 17 Register Information - 20 Package Information - 25 World Wide Sales Companies - 34 21130-DSH-001-B, 3/27/03

AD9763

Abstract: AD9763AST AD9763-EB AWG2021
Contextual Info: a FEATURES 10-Bit Dual Transmit DAC 125 MSPS Update Rate Excellent SFDR to Nyquist @ 5 mHz Output: 75 dBc Excellent Gain and Offset Matching: 0.1% Fully Independent or Single Resistor Gain Control Dual Port or Interleaved Data On-Chip 1.2 V Reference Single 5 V or 3 V Supply Operation

48-PIN

Abstract: AD9709 AD9709AST AD9709-EB AWG2021
Contextual Info: a FEATURES 8-Bit Dual Transmit DAC 125 MSPS Update Rate Excellent SFDR to Nyquist @ 5 MHz Output = 66 dBc Excellent Gain and Offset Matching: 0.1% Fully Independent or Single Resistor Gain Control Dual Port or Interleaved Data On-Chip 1.2 V Reference Single 5 V or 3 V Supply Operation

power607

Abstract: POWR607 24v Power Distribution Board Power1014 Power1220AT8 POWR1220AT8 power distribution board type 1 12V to 48V DC-DC Converter POWR1014 buffer 24V
Contextual Info: Power Manager II & ispClock Applications Power Manager and ispClock are two In-System Programmable mixed signal product families from Lattice Semiconductor. Each of these devices provide cost effective, standardized solutions across a wide range of applications which traditionally require

SMA200UP

Abstract: AD9767-EBZ
Contextual Info: FEATURES FUNCTIONAL BLOCK DIAGRAM 10-/12-/14-bit dual transmit digital-to-analog converters DACs 125 MSPS update rate Excellent SFDR to Nyquist @ 5 MHz output: 75 dBc Excellent gain and offset matching: 0.1% Fully independent or single-resistor gain control

L510B

Abstract: L61A L110 L111 l413 l812 L410A L77A L711B L713
Contextual Info: Appl i cat i o n N ot e Designing High-Speed ATM Switch Fabrics by Using Actel FPGAs The recent upsurge of interest in Asynchronous Transfer Mode ATM is based on the recognition that it represents a new level of both speed and simplification in telecommunication networks. The most significant

SMA200UP

Abstract: db3p1 INP32 ad8055 T1-1TCUP AD9763 AD9765 AD9767
Contextual Info: 10-/12-/14-Bit, 125 MSPS Dual TxDAC+ Digital-to-Analog Converters AD9763/AD9765/AD9767 FEATURES FUNCTIONAL BLOCK DIAGRAM 10-/12-/14-bit dual transmit digital-to-analog converters DACs 125 MSPS update rate Excellent SFDR to Nyquist @ 5 MHz output: 75 dBc

AD8047

Abstract: AD9763 AWG2021
Contextual Info: 10-Bit, 125 MSPS Dual TxDAC+ Digital-to-Analog Converter AD9763 FUNCTIONAL BLOCK DIAGRAM 10-bit dual transmit DAC 125 MSPS update rate Excellent SFDR to Nyquist @ 5 MHz output: 75 dBc Excellent gain and offset matching: 0.1% Fully independent or single resistor gain control

PAL16L8 programming algorithm

Abstract: Intel N85C224 EP330 P85C220 n85c220 PAL20L8 programming specifications 16v8 programming IC PALCE16 palc20r 20V8
Contextual Info: in tj, 85C220/85C224-100, -80 AND -66 FAST REGISTERED SPEED TSU, TSo 8-MACROCELL PLDs These register optimized timing PLDs offer superior design features: • Low-Power, High-Performance Upgrade for SSI/MSI Logic and Bipolar PALs* High-Performance Systems

JUMO dtRON 304

Abstract: jumo dTRON 4 PT100 temperature sensor JUMO manual 70304 dtron 308 jumo dTRON 4.1 relay 230v EN100015 jumo TTL RS232 converter jumo pressure
Contextual Info: JUMO dTRON 316 JUMO dTRON 308 JUMO dTRON 308 JUMO dTRON 304 JdTRON 304 JdTRON 308 JdTRON 316 Compact Controller with program function B 70.3041.0 Operating Manual 06.05/00442056 Please read this Operating Manual before commissioning the instrument. Keep the manual in a

PAL16L8 programming algorithm

Abstract: N85C220 85C220 pal16r8 programming algorithm 85C224-66 D85C220-66 intel PLD d85c220 gal 16v8 programming algorithm
Contextual Info: in te i 85C220/85C224-100, -80 AND -66 FAST REGISTERED SPEED TSU, TS0 8-MACROCELL PLDs These register optimized timing PLDs offer superior design features: • Low-Power, High-Performance Upgrade for SSI/MSI Logic and Bipolar PALs* High-Performance Systems

5 DIGIT dvm

Abstract: J266 Arcom Arcom Control Systems arcom 12/16 LK1b D-50
Contextual Info: J266 PCAD 12/16H 2192-09062-000-000 PCAD12/16H 16-Channel 12-bit ADC Board Technical Manual Product Information Full information about other Arcom products is available via the Fax-on-Demand System, Telephone Numbers are listed below , or by contacting our WebSite in the UK at: www.arcom.co.uk or in the US at:

Contextual Info: 10-/12-/14-Bit, 125 MSPS Dual TxDAC+ Digital-to-Analog Converters AD9763/AD9765/AD9767 FEATURES FUNCTIONAL BLOCK DIAGRAM 10-/12-/14-bit dual transmit digital-to-analog converters DACs 125 MSPS update rate Excellent SFDR to Nyquist @ 5 MHz output: 75 dBc

C8380

Abstract: AD804 AD9765 AD97651 AD9765AST AD9765-EB
Contextual Info: a FEATURES 12-Bit Dual Transmit DAC 125 MSPS Update Rate Excellent SFDR to Nyquist @ 5 MHz Output: 75 dBc Excellent Gain and Offset Matching: 0.1% Fully Independent or Single Resistor Gain Control Dual Port or Interleaved Data On-Chip 1.2 V Reference Single 5 V or 3 V Supply Operation

Contextual Info: a Preliminary Technical Data FEATURES 8-Bit Dual Transmit DAC 125 MSPS Update Rate Excellent SFDR and IMD: 67 dBc Excellent Gain and Offset Matching: 0.1% Fully Independent or Single Resistor Gain Control Dual Port or Interleaved Data On-Chip 1.2 V Reference

L510B

Abstract: l815 l73a L61A L713 L-612 L814 l812 L313A AC105
Contextual Info: Application Note AC105 Designing High-Speed ATM Switch Fabrics by Using Actel FPGAs The recent upsurge of interest in Asynchronous Transfer Mode ATM is based on the recognition that it represents a new level of both speed and simplification in telecommunication networks. The most significant

mod 8 ring counter using JK flip flop

Abstract: ega to vga circuits q 1257 5v constant power supply lob transistor BR 8772 BR 8050 D 555 design guide BT 4840 CD 4081 Cmos 2 input and gate IC cell phones
Contextual Info: MF1567-01 STANDARD CELL / EMBEDDED ARRAY S1K70000 / S1X70000 Series 5V Tolerant DESIGN GUIDE NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.

D5C090-50

Abstract: 5C090 N5C090 5C060 74HC EP900 P5C090-60 intel PLD 290196 n5c090-50
Contextual Info: in tj 5C090 24-MACROCELL CMOS PLD • High-Performance LSI Semi-Custom Logic Alternative to Low-End Gate Arrays, TTL, and 74HC SSI and MSI Logic ■ 24 Macrocells with Programmable I/O Architecture; Up to 36 Inputs 12 Dedicated, 24 I/O or 24 Outputs ■ Programmable Output Registers. Can

T1-1TCUP

Abstract: SMA200UP AD9709 DS90LV048B
Contextual Info: 8-Bit, 125 MSPS, Dual TxDAC+ Digital-to-Analog Converter AD9709 FEATURES FUNCTIONAL BLOCK DIAGRAM 8-bit dual transmit digital-to-analog converter DAC 125 MSPS update rate Excellent SFDR to Nyquist @ 5 MHz output: 66 dBc Excellent gain and offset matching: 0.1%

92x79

Abstract: 5304 POWER SUPPLY IC driver cicuit diagram transistor BCA 308 computer schematic power supply circuit diagram circuit design truth table NAND gate 74 epson 2480 manual ic configuration of xnor gates PCB design guide
Contextual Info: GATE ARRAY S1L35000 Series DESIGN GUIDE S1L35000 Series DESIGN GUIDE st issue March,2000 D May, 2001 in Japan C A MF924-02 NOTICE No part of this material may be reproduced or duplicated in any from or by any means without the written permission of EPSON. EPSON reserves the right to make changes to this material without

C3582a-0-2

Abstract: AD9763 AD9763AST AD9763-EB AWG2021 transmission line transformer
Contextual Info: a FEATURES 10-Bit Dual Transmit DAC 125 MSPS Update Rate Excellent SFDR and IMD: 78 dBc Excellent Gain and Offset Matching: 0.1% Fully Independent or Single Resistor Gain Control Dual Port or Interleaved Data On-Chip 1.2 V Reference Single 5 V or 3 V Supply Operation

INP36

Abstract: INP30 an555 INP34 INP28 INP14 INP-24 AD9763 AN-555 TP10
Contextual Info: a AN-555 APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • 781/329-4700 • World Wide Web Site: http://www.analog.com Using the AD9709, AD9763, AD9765, AD9767 Dual DAC Evaluation Board By Steve Reine and Dawn Ostenberg GENERAL DESCRIPTION

Contextual Info: Ä ID W A M < & g DKlF [^ôiÆ ÂTB©M in te i M85C224 FAST 1-MICRON CHMOS 8-MACROCELL jaPLD Up to 22 Inputs 14 Dedicated & 8 I/O and 8 Outputs High-Performance, Low-Power Upgrade for SSI/MSI Logic and Bipolar PALs* in Intel386 , i486™, i860™, 80960 Series,