OUTP11 Search Results

CDCLVP2106

Abstract: QFN-40 weight
Contextual Info: CDCLVP2106 www.ti.com. SCAS887 – SEPTEMBER 2009 12 LVPECL Output, High-Performance Clock Buffer

AA30

Abstract: AA34 AB30 M21110 PRBS MSB NCN30
Contextual Info: M21110 17 x 17 3.2 Gbps Crosspoint Switch with Input Equalization Data Sheet Features - 4 Terminal Descriptions - 5 Specification Tables - 7 Functional Description - 17 Register Information - 21 Package Information - 28 World Wide Sales Companies - 37 21110-DSH-001-B, 3/27/03

Contextual Info: CDCLVP1216 www.ti.com . SCAS877A – MAY 2009 – REVISED JULY 2009 16 LVPECL Output, High-Performance Clock Buffer

outp32

Abstract: M21130 AA30 AA34 AB30 OUTP23 NCN30
Contextual Info: M21130 68 x 68 3.2 Gbps Crosspoint Switch with Input Equalization Data Sheet Features - 4 Terminal Descriptions - 5 Specification Tables - 8 Functional Description - 17 Register Information - 20 Package Information - 25 World Wide Sales Companies - 34 21130-DSH-001-B, 3/27/03

Contextual Info: CDCLVD2108 www.ti.com SCAS905C – OCTOBER 2010 – REVISED DECEMBER 2010 Dual 1:8 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2108 FEATURES 1 • • • • • • • • • • • • Dual 1:8 Differential Buffer Low Additive Jitter <300 fs RMS in

Vogad

Abstract: DBS800 MX806 VOGAD IC
Contextual Info: 3 , 0 M X * C O M , I N C V -S * - . 0 0 $ M tf , X 8 6 A AUDIO PROCESSOR Description The MX806A LMR audio processor is intended primarily to operate as the “Audio TerminaT of radio systems using the DBS 800 Digitaily-integrated Baseband Sub­ system. The MX806A half-duplex device has signal paths and level setting elements that

L510B

Abstract: L61A L110 L111 l413 l812 L410A L77A L711B L713
Contextual Info: Appl i cat i o n N ot e Designing High-Speed ATM Switch Fabrics by Using Actel FPGAs The recent upsurge of interest in Asynchronous Transfer Mode ATM is based on the recognition that it represents a new level of both speed and simplification in telecommunication networks. The most significant

CDCLVP2106

Contextual Info: CDCLVP2106 www.ti.com. SCAS887 – SEPTEMBER 2009 12 LVPECL Output, High-Performance Clock Buffer

Contextual Info: CDCLVP1216 SCAS877C – MAY 2009 – REVISED AUGUST 2011 www.ti.com 16 LVPECL Output, High-Performance Clock Buffer Check for Samples: CDCLVP1216 FEATURES DESCRIPTION • • • The CDCLVP1216 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL

Contextual Info: CDCLVP1216 SCAS877C – MAY 2009 – REVISED AUGUST 2011 www.ti.com 16 LVPECL Output, High-Performance Clock Buffer Check for Samples: CDCLVP1216 FEATURES DESCRIPTION • • • The CDCLVP1216 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL

Contextual Info: CDCLVD2108 www.ti.com SCAS905C – OCTOBER 2010 – REVISED DECEMBER 2010 Dual 1:8 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2108 FEATURES 1 • • • • • • • • • • • • Dual 1:8 Differential Buffer Low Additive Jitter <300 fs RMS in

Contextual Info: CDCLVD1212 www.ti.com SCAS901B – SEPTEMBER 2010 – REVISED JANUARY 2011 2:12 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1212 FEATURES 1 • • • • • • • • • • • • 2:12 Differential Buffer Low Additive Jitter: <300 fs RMS in

QFN-48 LAND PATTERN

Abstract: CDCLVP1216 CDCLVP1216RGZR CDCLVP1216RGZT QFN-48
Contextual Info: CDCLVP1216 www.ti.com . SCAS877A – MAY 2009 – REVISED JULY 2009 16 LVPECL Output, High-Performance Clock Buffer

CDCLVP1216

Abstract: CDCLVP1216RGZR CDCLVP1216RGZT QFN-48
Contextual Info: CDCLVP1216 www.ti.com . SCAS877A – MAY 2009 – REVISED JULY 2009 16 LVPECL Output, High-Performance Clock Buffer

CDCLVP2108

Abstract: CDCLVP2108RGZR CDCLVP2108RGZT QFN-48 QFN-48 LAND PATTERN QFN-48 footprint
Contextual Info: CDCLVP2108 www.ti.com . SCAS878A – MAY 2009 – REVISED JULY 2009 16 LVPECL Output, High-Performance Clock Buffer

Contextual Info: CDCLVD2108 www.ti.com SCAS905C – OCTOBER 2010 – REVISED DECEMBER 2010 Dual 1:8 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2108 FEATURES 1 • • • • • • • • • • • • Dual 1:8 Differential Buffer Low Additive Jitter <300 fs RMS in

Contextual Info: Product Folder Sample & Buy Support & Community Tools & Software Technical Documents CDCLVP1204 SCAS880D – AUGUST 2009 – REVISED JUNE 2014 CDCLVP1204 Four LVPECL Output, High-Performance Clock Buffer 1 Features 3 Description • • • The CDCLVP1204 is a highly versatile, low additive

QFN-48 LAND PATTERN

Contextual Info: CDCLVP2108 SCAS878B – MAY 2009 – REVISED AUGUST 2011 www.ti.com 16 LVPECL Output, High-Performance Clock Buffer Check for Samples: CDCLVP2108 FEATURES DESCRIPTION • • • The CDCLVP2108 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL

Contextual Info: Sample & Buy Product Folder Support & Community Tools & Software Technical Documents CDCLVP1216 SCAS877E – MAY 2009 – REVISED SEPTEMBER 2014 CDCLVP1216 16 LVPECL Output, High-Performance Clock Buffer 1 Features 3 Description • • • The CDCLVP1216 is a highly versatile, low additive

Contextual Info: Product Folder Sample & Buy Support & Community Tools & Software Technical Documents CDCLVP1204 SCAS880E – AUGUST 2009 – REVISED SEPTEMBER 2014 CDCLVP1204 Four LVPECL Output, High-Performance Clock Buffer 1 Features 3 Description • • • The CDCLVP1204 is a highly versatile, low additive

AGGA-2

Abstract: GLONASS SV6 357 AGGA ADSP21020 epoch sv24 sv5 357 GLONASS chip T7905E
Contextual Info: Purpose and Scope The purpose of this document is to describe the detailed functionality of the secondgeneration Advanced GPS/GLONASS ASIC, the T7905E also refered to as the AGGA-2 . It describes the functionality, its modes of operation, programming aspects,

40spq

Contextual Info: CDCLVD2106 www.ti.com SCAS902B – SEPTEMBER 2010 – REVISED JANUARY 2011 Dual 1:6 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2106 FEATURES 1 • • • • • • • • • • • • Dual 1:6 Differential Buffer Low Additive Jitter: <300 fs rms

Contextual Info: CDCLVD1212 www.ti.com SCAS901 – SEPTEMBER 2010 2:12 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1212 FEATURES 1 • • • • • • • • • • 2:12 Differential Buffer Low Additive Jitter: <300 fs RMS in 10 kHz to 20 MHz Low Output Skew of 50 ps Max

Contextual Info: CDCLVP2106 SCAS887A – SEPTEMBER 2009 – REVISED AUGUST 2011 www.ti.com 12 LVPECL Output, High-Performance Clock Buffer Check for Samples: CDCLVP2106 FEATURES DESCRIPTION • • • The CDCLVP2106 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL