IMS PCB Search Results

T425

Abstract: T400 T414 T800 T805 inmos transputer T425 T800 transputer IMST425
Contextual Info: IMS T425 32-bit transputer FEATURES 32 bit architecture 40 ns internal cycle time 25 MIPS peak instruction rate Pin compatible with IMS T805, IMS T800, IMS T400 and IMS T414 Debugging support 4 Kbytes on-chip static RAM System Services 100 Mbytes/sec sustained data rate to internal

Inmos t805

Abstract: IMS T805-G25S IMS T805-F25S IMS T800 T400 T414 T425 T800 T805 inmos T414
Contextual Info: IMS T805 32-bit floating-point transputer FEATURES Floating Point Unit 32 32 bit architecture 40 ns internal cycle time 25 MIPS peak instruction rate 3.6 Mflops (peak) instruction rate Pin compatible with IMS T800, IMS T425, IMS T400 and IMS T414 Debugging support

inmos T414

Abstract: inmos T400 12u-1919-g19 25f5 T400 600 inmos transputer T425 T400 clock T800 transputer AD T805 IMS T414
Contextual Info: IMS T400 Low cost 32-bit transputer FEATURES H 32 bit architecture H 50 ns internal cycle time H 20 MHz only H 20 MIPS peak instruction rate H 10 MIPS sustained instruction rate H Pin compatible with IMS T805, IMS T800, IMS T425 and IMS T414 H 2 Kbytes on-chip static RAM

Inmos t805

Abstract: T805 inmos inmos transputer B427 TRAM ims pcb
Contextual Info: IMS B427 8Mbyte Size 2 TRAM Reset Analyse NotError Link0 8Mbytes DRAM IMS T805 Link1 Link2 Link3 Terminated links Subsystem PAL SS Reset SS Analyse notSS Error FEATURES DESCRIPTION H 25MHz IMS T805 Transputer The IMS B427 is a compact size 2 TRAM offering

Contextual Info: ’My 22 Chapter 6 IMS T805 transputer mos* Engineering Data FEATURES 32 bit architecture 33 ns internal cycle time 30 MIPS peak instruction rate 4.3 Mflops (peak) instruction rate Pin compatible with IMS T800, IMS T425, IMS T400 and IMST414 Debugging support

AD T805

Abstract: B50R MEMAD11 T805 IMS T805-F25S IMST805 transputer Inmos t805 inmos transputer T225 inmos transputer T425
Contextual Info: 32-bit floating-point transputer FEATURES • 32 bit architecture ■ 40 ns internal cycle time ■ 25 MIPS peak instruction rate ■ 3.6 Mflops (peak) instruction rate ■ ■ Pin compatible with IMS T800, IMS T425, IMS T400 and IMS T414 Debugging support

T400 600

Abstract: IMS T414
Contextual Info: Low cost 32-bit transputer FEATURES • 32 bit architecture ■ 50 ns internal cycle time ■ 20 MHz only ■ 20 MIPS peak instruction rate ■ 10 MIPS sustained instruction rate ■ Pin compatible with IMS T805, IMS T800, IMS T425 and IMS T414 ■ 2 Kbytes on-chip static RAM

CQ 2AF1

Abstract: IMST425 IMS T400 Inmos T222
Contextual Info: 32-bit transputer FEATURES • 32 bit architecture ■ 40 ns internal cycle time ■ 25 MIPS peak instruction rate ■ Pin compatible with IMS T805, IMS T800, IMS T400 and IMS T414 ■ Debugging support ■ 4 Kbytes on-chip static RAM ■ 100 Mbytes/sec sustained data rate to internal

specifications of tdr

Abstract: Inmos t805 IMS processor
Contextual Info: SGS-THOMSON IMS T805 ’H E S m M M 32-bit floating-point transputer FEATURES • ■ ■ 32 bit architecture 40 ns internal cycle tim e 25 M IPS peak instruction rate ■ 3.6 M flops (peak) instruction rate ■ Pin co m patible w ith IMS T800, IMS T425, IMS T400

Module Motherboard Software MMS

Abstract: 16 stage pipeline
Contextual Info: Chapter 42 _ 361 IMS B012 Double extended eurocard anmos* FEATURES • 16 transputer module TRAM slots • IMS T222 - 16 bit transputer • Two IMS C004 programmable 32 way switches • Double Extended Eurocard • 40 links available at edge connectors

Contextual Info: S G S -1 H 0 M S 0 N « t i m i I g ï M a M Ê IMS T400 i Low cost 32-bit transputer FEATURES 32 bit architecture 50 ns internal cycle time 20 MHz only 20 MIPS peak instruction rate 10 MIPS sustained instruction rate Pin compatible with IMS T805, IMS T800, IMS T425

inmos T414

Abstract: IMS T414 T414 inmos transputer T425 IMSB401 T800 transputer inmos transputer IMSB008 T800 IMST414
Contextual Info: Chapter 17 149 IMS B401 TRAM 32-bit transputer 32 Kbytes Size 1 □ m os Engineering Data Reset Analyse-NotError ^ o /j- IMS T800 LinkO -«- h * or Linkl - - H , IMS T425 32 Kbytes SRAM Link2 Link3. Terminated links FEATURES GENERAL DESCRIPTION

B-428

Contextual Info: Chapter 22 181 IMS B428 32-bit transputer 2 Mbytes Size 2 TRAM mos Engineering Data Reset Refresh control Analyse <h NotError LinkO - Address IMS T801 L in kl - I Data Link2 L¡nk3 - 4 1 Subsystem port FEATURES IMS T801 Transputer with non-multiplexed buses

sbl 20100

Abstract: T425-X25S MEMAD11 inmos transputer T425
Contextual Info: ^•7 # DMD g(fii ilL[l(gTO©[i!!in(gI / = T S G S -T H O M S O N IM S T 4 2 5 32-bit transputer FEATURES ■ 32 bit architecture ■ 40 ns internal cycle time ■ 25 MIPS peak instruction rate ■ Pin compatible with IMS T805, IMS T800, IMS T400 and IMS T414

IMST414

Abstract: IMS T400 ST T4 1060 0922 imst400 IMST225 inmos T414 T805-20 R3174 si9590 inmos transputer
Contextual Info: SGS-THOMSON IM S T 4 0 0 Low cost 32-bit transputer FEATURES • 32 bit architecture ■ 50 ns internal cycle time ■ 20 MHz only ■ 20 MIPS peak instruction rate ■ 10 MIPS sustained instruction rate ■ Pin compatible with IMS T805, IMS T800, IMS T425

EIA-343

Abstract: G300B B-419 g300 video b419
Contextual Info: Chapter 30 243 I M S B 4 1 9 Integrated graphics TRAM Size 6 OinimOS' Engineering Data FEATURES GENERAL DESCRIPTION • The IMS B419 incorporates the IMS G300B Co­ lour Video Controller CVC with the IMS T800 32 bit Floating Point Transputer to form a high per­

T800 transputer

Abstract: T800 INMOS T800 2512 package resistor dimensions details Inmos inmos static ram
Contextual Info: Chapter 25 203 IMS B427 mos 32-bit transputer 8 Mbytes Size 2 TRAM Engineering Data FEATURES GENERAL DESCRIPTION • 25MHz IMS T800 Transputer • 8 Mbyte of one wait-state DRAM 160 ns memory cycle time The IMS B427 Is a compact size 2 TRAM offering 8Mbytes of 4-cycle DRAM and subsystem

inmos T400

Abstract: T400-T20S AD1230 T4-0065 800-00030 T400-J20S AD123 inmos transputer reference manual imst400
Contextual Info: iZ J S G S -T H O M S O N ^ 7 # . » » I U I © « » IM S T 4 0 0 ® 32 bit transputer FEATURES 32 bit architecture 50 ns internal cycle time 20 MHz only 20 MIPS peak instruction rate 10 MIPS sustained instruction rate Pin compatible with IMS T805, IMS T800, IMS T425

t425

Abstract: SGS thomson power schottky 8000000C sgs thomson 23-F1 KJH T6 IMST425 inmos transputer T425
Contextual Info: w # S G S -T H O M S O N IM < 5 , kT # D ïiin g M iiiL iK g T Â E g n e i ,M & _ T 4 2 5 32-bit transputer FEATURES 32 bit architecture 40 ns internal cycle time 25 MIPS peak instruction rate Pin compatible with IMS T805, IMS T800, IMST400 and IMS T414

coaxial cable UT-85

Contextual Info: SMP connectors the easy connection SMP from IMS Connector Systems The SMP connectors product line from IMS Connector Systems includes a full range of PCB plugs for SMD technology as well as for traditional throughhole mounting in Smooth Bore and Limited Detent versions. The connectors have

B433

Abstract: motherboard imst805 INMOS
Contextual Info: w m S C S " T H O M S O N im ^ R 4 ^ Size 4 16Mbyte HTRAM FEATURES DESCRIPTION • IMS T805 25 MHz Transputer The IMS B433 uses the IMS T805 25MHz trans­ puter. The 16 Mbytes of single w ait-state DRAM is sufficient to run large applications. Also pro­ vided is 64 Kbytes of fast SRAM 3 cycle , so any

ic t805

Abstract: IMS T805-F20E inmos transputer inmos transputer T225 T425 T800 t225 Inmos t805 IMS T805-G20E MEMAD11
Contextual Info: SGS-THOMSON IMS T805E •HI 32-bit floating-point transputer - Extended temperature EATURES 32 bit architecture 50 ns internal cycle time 20 MIPS peak instruction rate 2.8 Mflops (peak) instruction rate Pin compatible with IMS T800 Floating Point Unit Debugging support

1.5mm 5 pin connector

Abstract: RF connector connector pcb mounted RF PCB Antenna thermal pcb guidelines Sarantel geohelix antenna
Contextual Info: GeoHelix -P2 GPS Antenna IMS Connector Installation and Usage Guidelines Sarantel Ltd Unit 2, Wendel Point Ryle Drive Park Farm South Wellingborough NN8 6BA UK +44 1933 670560 info@sarantel.com www.sarantel.com GeoHelix-P2 IMS Connector Installation and Usage Guidelines

7F60

Abstract: T222-20
Contextual Info: Chapter 33 283 IMS B422 SCSI TRAM Size 2 mos Engineering Data 64 Kbytes SRAM Reset- ► Analyse- *NotError LlnkO —I _I— Linkl —I_ H Link2 H b Llnk3 - I h- SCSI Bus IMS T222 SSReset SSAnalyse notSSError FEATURES GENERAL DESCRIPTION