IDT71981 Search Results

2S701

Abstract: ATA 2388 IC ATA 2388 2L85 719b1
Contextual Info: CMOS STATIC RAMs 64K 16Kx 4-BIT IDT71981S/L IDT71982S/L Separate Data Inputs and Outputs Integrated Device Technology, Inc. FEATURES: • • • • • • • • • • Separate data inputs and outputs IDT71981S/L: outputs track inputs during write mode

TAA 981

Abstract: IDT71982 71982
Contextual Info: CMOS STATIC RAMs 6 4 K 1 6 K x 4-BIT IDT71981S/L IDT71982S/L Separate Data Inputs and Outputs In te g rate d D e vic e Technology, In c . FEATURES: • • • • • • • • • • S eparate data inputs and outputs ID T71981S /L: ou tputs tra c k inputs during w rite mode

2S5570

Abstract: 2S8521
Contextual Info: INTEGRATED DEVICE BflE D • 4 fi2 5 7 7 1 □00Ö333 ? H ID T T CMOS STATIC RAMS 6 4 K 1 6 K x 4-BIT - IDT71981S/L IDT71982S/L Separate Data Inputs and Outputs Integrated Device Technology, Inc* FEATURES: • Optimized for fast RISC processors including the

Contextual Info: CMOS STATIC RAMS 64K 16Kx 4-BIT IDT71981S/L IDT71982S/L Separate Data Inputs and Outputs Integrated Device Technology, Inc. FEATURES: • Optim ized for fast R IS C processors including the ID T 7 9R 300 0 • S eparate d ata inputs and outputs • ID 171981S /L: outputs track inputs during write mode

ATT7C162

Contextual Info: Data Sheet January 1992 = sA T & T Microelectronics ATT7C161 ATT7C162 High-Speed CMOS SRAM 64 Kbit 16K x 4 , Separate I/O Features • Plug-compatible with IDT71981/71982 and CY7C161/162 ■ High speed — 10 ns maximum access time ■ Low-power operation

Contextual Info: I CM O S STATIC RAMS 6 4 K 1 6 K X 4-BIT ID T71981S /L ID T71982S /L S eparate Data Inputs and Outputs FEATURES: DESCRIPTION: • S eparate d a ta inp u ts a n d o u tp u ts • IDT71981S/L: o u tp u ts tra ck inp u ts d u rin g w rite m ode • IDT71982S/L: h ig h im p e d a n c e o utp u ts d u rin g w rite m ode

Contextual Info: Data Sheet March 1992 ATT7C161 ATT7C162 , =ATaT Microelectronics High-Speed CMOS SRAM 64 Kbit 16K x 4 , Separate I/O Features • Highspeed— 10 ns maximum access time ■ Plug-compatible with IDT71981/71982 and CY7C161/162 ■ Separate I/O and transparent write (ATT7C161) or

2S5570

Contextual Info: CMOS STATIC RAMs 64K 16Kx 4-BIT IDT71981S/L IDT71982S/L Separate Data Inputs and Outputs Integrated Device Technology, Inc. FEATURES: • • • • • • • • • • Access times as fast as 15ns are available. These circuits also offer a reduced power standby mode (Isb). When CSi or

Z980

Abstract: 71m1 2L20 IDT71981
Contextual Info: CMOS STATIC RAMS 64K 16K x 4-BIT IDT71981S/L IDT71982S/L Separate Data Inputs and Outputs Integrated Device Technology, Inc. FEATURES: • Optimized for last RISC processors including the IDT79R3000 • Separate data inputs and outputs • ID171981S/L: outputs track inputs during write mode

L282

Abstract: 2S701
Contextual Info: I N T E G R A T E D D E VI CE SÛE J> m 405 5 77 1 0 0 1 1 b 3 0 CMOS STATIC RAMs 64K 16K X 4-BIT T'iä m i T > T IDT71981S/L IDT71982S/L Separate Data Inputs and Outputs FEATURES: • • • • • • • • • • Separate dala inputs and outputs

Contextual Info: Integrated Device Technolog y Inc 128K x 8 SRAM WITH REGISTERED ADDRESS LINES, LATCHED /BUFFERED DATA!N LINES AND REGISTERED DATA out LINES FEATURES: • Registered address lines • Latched and Buffered Input data lines • Registered output data lines • Separate I/O

L39c

Abstract: IDT49C403 signal path designer
Contextual Info: HIGH SPEED 16-BIT REGISTER WITH SPC ^IDT49FCT618 ?49FC T618A id FEATURES: DESCRIPTION: • High-speed non-inverting 16-bit parallel data register for any data path, control path or pipelining application • Read back path from the data output back to the data input

C3264

Abstract: RAM-6A
Contextual Info: 128K x 8 SRAM WITH LATCHED/ BUFFERED ADDRESS LINES, REGISTERED DATA|N LINES AND LATCHED/BUFFERED DATA0UT LINES IDT7M822 CS and WE data that meets the specified set-up time will be latched when LE goes low. DATA in is controlled by its own clock, CPDIN. When ENDIN

C3264

Contextual Info: INT EGR AT ED DEVICE T7 4 8 2 5 7 7 1 I NTEGRATED Integrated DeviceTechn0t03y. Inc. D E | 4ÖSS771 DDOaflDB 0 | DE V I C E 97D 02803 ^- T -4 6 -2 3 -1 4 IDT7M827 128K x 8 SRAM WITH REGISTERED ADDRESS LINES, LATCHED /BUFFERED DATA!N LINES AND REGISTERED DATA0Ut l,NES

ADA01

Abstract: ADA10 Adb4
Contextual Info: H T, Integrated DeviœTèchnology Inc DUAL MULTIPLEXED 16K x 20 SYNCHRONOUS STATIC RAM MODULE FEATURES: • Dual 16K x 20 syn ch ro n o u s RAM • E d g e trig g e re d d ata in p u t a n d data o u tp u t registers • E dge trig g e re d d ata a ddress registers

IDT39C60

Abstract: 74FCT245 1002d AN-24 IDT49C460 IDT71256 IDT74FCT245 IDT74FCT646
Contextual Info: DESIGNING WITH THE IDT49C460 AND IDT39C60 ERROR DETECTION AND CORRECTION UNITS  Integrated Device Technology, Inc. APPLICATION NOTE AN-24 DESIGNING WITH THE IDT49C460 AND IDT39C60 ERROR DETECTION AND CORRECTION UNITS APPLICATION NOTE AN-24 By Robert Stodieck

IDT39C60

Abstract: 1002B 74FCT245 AN-24 IDT49C460 IDT71256 IDT74FCT245 IDT74FCT646 1002d
Contextual Info: DESIGNING WITH THE IDT49C460 AND IDT39C60 ERROR DETECTION AND CORRECTION UNITS Integrated Device Technology, Inc. DESIGNING WITH THE IDT49C460 AND IDT39C60 ERROR DETECTION AND CORRECTION UNITS INTRODUCTION APPLICATION NOTE AN-24 APPLICATION NOTE AN-24 By Robert Stodieck

Contextual Info: 128K x 8 SRAM WITH REGISTERED ADDRESS LINES, REGISTERED DATA!N LINES AND LATCHED/BUFFERED DATA o u t LINES Address, Write Enable W E and the three Chip Select (CS) lines are controlled by CP. W hen CE (clock enable) is asserted, all address, C S a n d W E data that m eetsthe specified set-up time will

Contextual Info: 128K x 8 SRAM WITH REGISTERED ADDRESS LINES, AND REGISTERED DATA LINES A ddress, W rite E nable W E and th e th re e C hip S elect (CS) lin e s a re co n tro lle d b y CP. W hen C E (c lo c k enable) is asserted, all address, C S a n d W E d ata th a t m eets th e sp e c ifie d set-up tim e w ill

STATIC RAM 8464

Abstract: IMS1433 SSM6116 IMS1630 SSM6171 SSM7188 hitachi selection guide SSM7164 hm6264 ic 6116 ram
Contextual Info: 16K Product S e le c tio n -C ro s s Reference Guide 16K Static RAM — Product Selection Typical Power mW Maximum Speed (ns) Part No/'» L7C167 Description Packages Available121 Com. Mil. Oper. Inactive Pins 8 10 135 75 20 DIP, LCC SOIC (Gull-Wing) SOJ (J-Lead)

IDT71961L-15

Abstract: IDT71981L-55 IDT71981L-70 IDT71981S-45 IDT71981S-55 IDT71981S-70 IDT71982L-45 IDT71982L-55 IDT7198L35 MB81C75-25
Contextual Info: - 76 6 4 K -Í X m % CC y CMOS -f- y 7 TAAC max ns) TCAC max (ns) TOE max (ns) TOH min (ns) TOD max (ns) TWP min (ns) 20 S t a t i c RAM ( 1 6 3 8 4 x 4) m tî 1$ TDS rain (ns) TDH min (ns) TWD min (ns) TWR max (ns) V D D or V C C (V) 2 4 P I N 6 4 E 4 À

Contextual Info: 1 MEGABIT 128K x 8 REGISTERED/BUFFERED/ LATCHED CMOS STATIC RAM SUBSYSTEMS IDT7M824 FAMILY FEATURES: DESCRIPTION: • High-density 1024K-bit (128K x 8-bit) CMOS static RAM modules with registered/buffered/latched addresses and l/Os The IDT7M824 fam ily is a set of 1024K-bit (128K x 8-bit) high­

Contextual Info: INT EG RAT ED DEVICE T7 dË J 482577 1 INTEGRATED DEVICE MÖHS771 ODOSÖDÜ 4 97D 0 2800 T -4 6 -2 3 -1 4 Integrated DeviceTechnology Inc. 128K x 8 SRAM WITH REGISTERED IDT7M826 ADDRESS LINES, REGISTERED DATA.m LINES AND LATCHED/BUFFERED DATA0UT LINES 53

S498

Contextual Info: | dt Integrated DeviceTechnology, Inc CMOS STATIC RAMS 64K 16Kx 4-BIT) IDT 71981S/L IDT 71982S/L Separate Data Inputs and Outputs FEATURES: DESCRIPTION: • T h e ID T71981/ID T 71982are 65,536-blt h ig h -sp ee d static RAMs o rga n ized as 16K x 4. T h e y are fa b rica ted u sin g ID T’s highperform ance, h ig h -re lia b ility te c h n o lo g y -C E M O S . T h is state-ofthe-art te ch n o lo g y, c o m b in e d w ith innovative c irc u it desig n te ch ­