ICS810001 Search Results

Contextual Info: FemtoClock Dual VCXO Video PLL ICS810001I-21 DATASHEET General Description Features The ICS810001I-21 is a PLL based synchronous clock generator that is optimized for digital video clock jitter attenuation and frequency translation. The device contains two internal frequency

VCXO 27MHZ HSYNC

Abstract: 810001DK-21LF
Contextual Info: PRELIMINARY ICS810001-21 FEMTOCLOCKS DUAL VCXO VIDEO PLL General Description Features The ICS810001-21 is a member of the HiperClockS™ family of high performance clock solutions from IDT. HiPerClockS™ The ICS810001-21 is a PLL based synchronous clock generator that is optimized for digital video

ICS810001-21

Abstract: ICS810001 810001BK-21 VCXO 27MHZ HSYNC 1080P ITU-R601 2222na
Contextual Info: PRELIMINARY Integrated Circuit Systems, Inc. ICS810001-21 FEMTOCLOCKS DUAL VCXO VIDEO PLL GENERAL DESCRIPTION FEATURES The ICS810001-21 is a member of the HiperClockS™ family of high performance clock HiPerClockS™ solutions from ICS. The ICS810001-21 is a PLL

digital metal detector

Abstract: 30MHZ HC49 ICS810001-21 ICS810001DK-21 MO-220
Contextual Info: ICS810001-21 FEMTOCLOCK DUAL VCXO VIDEO PLL General Description Features The ICS810001-21 is a member of the HiperClockS™ family of high performance clock solutions from IDT. HiPerClockS™ The ICS810001-21 is a PLL based synchronous clock generator that is optimized for digital video

ICS810001-21

Abstract: VCXO 74.25MHZ 1080P ITU-R601 74125 logic diagram X22 3A ics81000 SMPTE 1080p level a 74125 ic pin diagram
Contextual Info: DATA SHEET PRELIMINARY Integrated FEMTOCLOCKS DUAL VCXO Circuit VIDEO PLL Systems, Inc. ICS810001-21 ICS810001-21 FEMTOCLOCKS™ DUAL VCXO VIDEO PLL GENERAL DESCRIPTION FEATURES The ICS810001-21 is a member of the HiperClockS™ family of high performance clock

ICS810001DK-21

Abstract: 810001DK-21LF 810001DK-21 ICS810001-21 30MHZ HC49 MO-220
Contextual Info: FemtoClock Dual VCXO Video PLL ICS810001-21 DATA SHEET General Description Features The ICS810001-21 is a PLL based synchronous clock generator that is optimized for digital video clock jitter HiPerClockS™ attenuation and frequency translation. The device

ICS810001-22

Abstract: SCHEMATIC POWER SUPPLY TRANSISTOR 7313 smd data sheet HC49 ICS0001B22L ICS810001BK-22 MO-220 53946-1 3F smd transistor crystal oscillator smd 162mhz
Contextual Info: FemtoClock Dual VCXO Video PLL ICS810001-22 DATA SHEET General Description Features The ICS810001-22 is a member of the HiperClockS™ family of high performance clock solutions from IDT. HiPerClockS™ The ICS810001-22 is a PLL based synchronous clock

Contextual Info: PRELIMINARY Integrated Circuit Systems, Inc. ICS810001-21 FEMTOCLOCKS DUAL VCXO VIDEO PLL GENERAL DESCRIPTION FEATURES The ICS810001-21 is a member of the HiperClockS™ family of high performance clock HiPerClockS™ solutions from ICS. The ICS810001-21 is a PLL

Contextual Info: FemtoClock Dual VCXO Video PLL ICS810001-21 DATA SHEET General Description Features The ICS810001-21 is a PLL based synchronous clock generator that is optimized for digital video clock jitter HiPerClockS™ attenuation and frequency translation. The device

ICS275-22

Abstract: 150-0320610-B1 RX-2 27MHz 720P59 332-5HB01-0AB0 734 coaxial cable data hsmc connector IC TX-2 ICS810001-21 BNC connector FOOT PRINT
Contextual Info: SDI HSMC Reference Manual 101 Innovation Drive San Jose, CA 95134 www.altera.com Document Version: Document Date: 1.0 July 2009 Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

D10.2 pattern

Contextual Info: Serial Digital Interface Reference Design for Arria II GX Devices AN-601-1.3 Application Note The Serial Digital Interface SDI reference design shows how you can transmit and receive video data using the Altera SDI MegaCore® function and the Arria® II GX

differential SMA connectors

Abstract: AN609 27mhz transmitter and receiver J17-J18 SDI HSMC SDI pattern generator
Contextual Info: Serial Digital Interface Reference Design for Cyclone IV Devices AN-641-1.2 Application Note The Serial Digital Interface SDI reference design shows how you can transmit and receive video data using the Altera SDI MegaCore® function and the Cyclone® IV GX

hd sdi receiver

Abstract: SDI INTERFACE hd-SDI EPM2210 MAX1619 hd sdi Transmitter alt4gxb 50 MHz xtal block diagram of digital audio section to lcd monitor 3G-SDI
Contextual Info: AN 600: Serial Digital Interface Reference Design for Stratix IV Devices AN-600-1.1 July 2010 The Serial Digital Interface SDI reference design shows how you can transmit and receive video data using the Altera SDI MegaCore® function and the Audio Video

Contextual Info: Serial Digital Interface Reference Design for Stratix V GX and Arria V GX Devices AN-668 Application Note Introduction The Serial Digital Interface SDI reference design shows how you can transmit and receive video data using the Altera SDI MegaCore® function, with the Stratix® V GX

SDI INTERFACE

Abstract: Arria II GX FPGA Development Board hd sdi Transmitter 27mhz transmitter AN558 EPM2210 hd sdi receiver SDI pattern generator AN587
Contextual Info: AN 601: Serial Digital Interface Reference Design for Arria II GX Devices AN-601-1.2 May 2010 The Serial Digital Interface SDI reference design shows how you can transmit and receive video data using the Altera SDI MegaCore® function and the Arria® II GX

Contextual Info: Serial Digital Interface Reference Design for Stratix IV Devices AN-600-1.2 Application Note The Serial Digital Interface SDI reference design shows how you can transmit and receive video data using the Altera SDI MegaCore® function and the Audio Video

Contextual Info: Terasic THDB-SUM SDI HSMC Terasic SDI HSMC Board User Manual Document Version 1.00 Document Version 1.00 AUG 21, Aug. 20 2009 by Terasic Introduction Page Index INTRODUCTION. 1