IC 74 LS 138 DECODER DATA SHEET Search Results

TC74LCX138F

Abstract: TC74LCX138FK TC74LCX138FN TC74LCX138FT VSSOP16-P-0030-0
Contextual Info: TC74LCX138F/FN/FT/FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic Low-Voltage 3-to-8 Line Decoder with 5-V Tolerant Inputs and Outputs The TC74LCX138 is a high-performance CMOS 3-to-8 decoder.

Contextual Info: ADVANCE MICRON8 I 32 MEG X 72 REGISTERED SDRAM DIMM TEOWOLOOV, INC. MT18LSDT3272 SYNCHRONOUS DRAM MODULE F o r the late st data sheet revisions, plea se re fe r to the Micron Web site: w w w .m icron.com /m ti/m sp/htm l/datasheet.htm l FEATURES PIN ASSIGNMENT Front View

Contextual Info: ADVANCE MICRON1 32 M EGx72 I SDRAM DIMM SYNCHRONOUS DRAM MODULE M T 18L S D T 3272A F o r the late st data sheet revisions, plea se re fe r to the Micron Web site: w w w .m icron.com /m ti/m sp/htm l/datasheet.htm l FEATURES PIN ASSIGNMENT Front View 168-Pin DIMM

Contextual Info: LATTICE SEMICONDUCTOR Lattica bûE D • 5301^4= 0QG27Ü7 b4T HILA T pLSI and ispLSI 3256 High Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — — — — — High Speed Global Interconnect 128 I/O Pins

Zoran 888

Abstract: UV618 Zoran ZR36120 ZR36110 ZR36120 CS4920 SAA2502 SAA7110 SAA7111 SAA7188
Contextual Info: < lllk ZR36120 Multimedia Controller for PCI Bus Data Sheet Features • Glueless interface to PCI bus. PCI spec. 2.1 compliance . I C bus master port. ■ Glueless interface to MPEG decoders (e.g., ZR36100/ ZR36110), video digitizers (e.g., SAA 7110, SAA 7111),

Contextual Info: XRT7300 E3/DS3/STS-1 Line Interface Unit January 2000 FEATURES l Single-chip Transmit and Receive Line Interface IC for E3 34.368Mbps , DS3 (44.736Mbps) and SONET STS-1 (51.84Mbps) Applications l l Transmit Interface Characteristics l Accepts Either Single Rail or Dual Rail Data

A1013 equivalent

Abstract: HSP45116 HSP45116GC-15 HSP45116GC-25 HSP45116GC-33 HSP45116GI-15 HSP45116GI-25 HSP45116GI-33 HSP45116VC-15 HSP45116VC-25
Contextual Info: HSP45116 Data Sheet May 1999 File Number Numerically Controlled Oscillator/Modulator Features The Intersil HSP45116 combines a high performance quadrature Numerically Controlled Oscillator NCO and a high speed 16-bit Complex Multiplier/Accumulator (CMAC)

Contextual Info: Preliminary Data Sheet November 1997 m icroelectro nics group L u c m t T a d m o lo g lM Ball Labi In rn w tk m ORCA OR3Cxx 5 V and OR3Txxx (3.3 V) Series Field-Programmable Gate Arrays Features • High-performance, cost-effective, 0.35 |am 4-level metal technology, with a migration plan to 0.25 |am

Contextual Info: Preliminary Information 20695G /0-M arch 1998 AMD£I AMD-K6" Processor Data Sheet About This Data Sheet The AMD-K6 Processor Data Sheet supports the Model 6 and M odel 7 versions of the AMD-K6 p rocessor fam ily. M odel 6 refers to th e AMD-K6 m anufactured in the

Contextual Info: I =¥= = = = ’= IBM13N4649JC IBM13N4739JC PRELIM INARY 4M x 64/72 2 Bank Unbuffered SDRAM Module Features • 168 Pin emerging JEDEC Standard, Unbuffered 8 Byte Dual In-line Memory Module • 4Mx64/72 Synchronous DRAM DIMM • Performance: CAS Latency

TTL 7400

Abstract: transistor SI 6822 application notes signetics 74LS00 gate fairchild dtl pj 939 diode 7410 IC pj 939 lv bq 8050 ac servo controller schematic
Contextual Info: FAIRCHILD FAST' Applications Handbook A S chlum berger C om pany 1987 Fairchild Semiconductor Corporation, Digital Unit 333 Western Avenue, South Portland, Maine 04106 207/775-8700 TWX 710-221-1980 FAST Fairchild Advanced Schottky TTL is a registered trademark of

Contextual Info: 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING POINT UNIT • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ Built-In Interrupt Controller — 31 Priority Levels, 256 Vectors

100 qfp 14 x 14

Contextual Info: Freescale Semiconductor, Inc. Data Sheet: Technical Data K24P144M120SF5 Rev 3, 04/2014 Kinetis K24F Sub-Family Data Sheet 120 MHz ARM Cortex®-M4-based Microcontroller with FPU MK24FN1M0VLQ12 MK24FN1M0VLL12 MK24FN1M0VDC12 The K24 product family features high memory densities, low

Contextual Info: Lattice ispLSI 6192 " ; Semiconductor • ■ ■ Corporation High Density Programmable Logic wjth Dedicated Memory and Register/Counter Modules — 96 I/O Pins with Input Registers — Security Cell Prevents Unauthorized Design C opy­ ing Features • A FAMILY OF HIGHLY INTEGRATED, CELL-BASED,

Fairchild dtl catalog

Abstract: johnson and ring counter using ic 7495 equivalent of transistor 9014 NPN 4 bit bcd adder pin diagram and truth table using ic 7483 MIL-STD-806 alu 9308 d Fairchild 9300 NL940 Fairchild msi full subtractor circuit using ic 74153 multiplexer
Contextual Info: FAIRCHILD SEMICONDUCTOR THE TTL APPLICATIONS HANDBOOK THE TTL APPLICATIONS HANDBOOK Prepared by the Digital Applications Staff of Fairchild Semiconductor Edited by Peter Alfke and lb Larsen FAIRCHILD S E M IC O N D U C T O R 464 Ellis Street, M ountain View, California 94042

Contextual Info: AM DÌ1 AMD-K6 -2 Processor Data Sheet •• • - , - v . • Preliminary Information AMD-K6-2 Processor Data Sheet AMD£J 1999 Advanced Micro Devices, Inc. A ll rights reserv ed . The contents of this docum ent are provided in connection w ith A dvanced Micro

A1013 equivalent

Abstract: detail of half adder ic ic number of half adder A1013 transistors phase shifter 10MHz digital phase shifter mhz half adder 74 Analog Multiplier for am modulation half adder ic number Numerically Controlled Oscillator
Contextual Info: NS E SI G D NE W CT FO R P R O D U D E EN D U TE O M M U B STI T 6 A C E S R LE 4511 NOT Data SIBSheet H SP PO S HSP45116 July 2004 FN2485.8 Numerically Controlled Oscillator/Modulator Features The Intersil HSP45116 combines a high performance quadrature Numerically Controlled Oscillator NCO and a

Contextual Info: Data Sheet June 1999 microelectronics group Lucent Technologies Bell Labs Innovations ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • High-performance, cost-effective, 0.35 pm OR3C and 0.3 pm (OR3T) 4-level metal technology, (4- or 5-input

0257S2

Contextual Info: AMD-K6-III Processor Data Sheet AMD Z\ D i 02575E5 QDLBE72 41fl B 1999 Advanced Micro Devices, Inc. A ll rig h ts reserv ed . The contents of this docum ent are provided in connection w ith A dvanced Micro D evices, Inc. "AMD" products. AMD m akes no representations or w arranties w ith

Contextual Info: Preliminary Information AMD-K6 -2 Processor Data Sheet 21850F/0—February 1999 1 AMD£I AMD-K6®-2 Processor • A dvanced 6-Issue RISC86® S uperscalar Micro arch itectu re ♦ Ten p a ra lle l specialized execution un its ♦ M ultiple sophisticated x86-to-RISC86 in stru ctio n decoders

Transistor BC 227

Contextual Info: VPX 3225D, VPX 3224D PRELIMINARY DATASHEET Contents Page Section Title 6 1. Introduction 7 1.1. System Architecture 8 2. Functional Description 8 2.1. Analog Front-End 8 2.1.1. Input Selector 8 2.1.2. Clamping 8 2.1.3. Automatic Gain Control 8 2.1.4. Analog-to-Digital Converters

Contextual Info: AMDÌ1 PRELIMINARY Élan SC300 Highly Integrated, Low-Power, 32-Bit Microcontroller DISTINCTIVE CHARACTERISTICS - Zero wait-state access with 70 ns, Page mode DRAMs • Highly integrated, single-chip CPU and system logic - Supports up to 16 Mbyte system memory

Contextual Info: áç XRT83SL34 PRELIMINARY QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR JANUARY 2003 REV. P1.0.6 GENERAL DESCRIPTION The XRT83SL34 is a fully integrated Quad four channel short-haul line interface unit for T1 (1.544Mbps) 100Ω, E1 (2.048Mbps) 75Ω or 120Ω, or

PCNETISA -KT/2

Contextual Info: P RE LIM INARY a Advanced Micro Devices Am79C965 PCnet -32 Single-Chip 32-Bit Ethernet Controller DISTINCTIVE CHARACTERISTICS • Single-chip Ethernet controller for 386DX, 486, and Video Electronics Standards Association VESA local buses ■ Supports ISO 8802-3 (IEEE/ANSI 802.3) and