HD74ACT Search Results

Contextual Info: HM66205 S e rie s-524,288-Word x 8-Bit High Density CM O S Static RAM Module • PIN ARRANGEMENT Description The HM66205 is a high density 4M-bit static RAM module consisting of 4 pieces HM628128LTS products TSOP type 1M static RAM and a HD74ACT138FP equivalent product (SOP

Contextual Info: HD74AC138/HD74ACT138 Description • 1 - o f- 8 Decoder/Demultiplexer Pin Assignment The HD74AC138/HD74ACT138 is a high-speed l-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow

Contextual Info: H D 74A C 253/H D 74A C T 253* Description The HD74ACa53/HD74ACT253 is a dual 4-input multiplexer with 3-state outputs. It can select two bits of data from four sources using common select inputs. The outputs may be individually switched to a high impedance state with a High on the

Zo transistor h07

Contextual Info: H D 74A C 14/H D 74A C T14 • H e x Inverter Schmitt Trigger Description The HD74AC14/HD74ACT14 contains six logic in­ verters which accept standard CMOS input signals TTL levels for HD74ACT14 and provide standard CMOS output levels. They are capable of trans­

DP-14

Abstract: FP-14DA FP-14DN HD74AC86 HD74ACT86 TTP-14D Hitachi DSA003769
Contextual Info: HD74AC86/HD74ACT86 Quad 2-Input Exclusive-OR-Gate Features • Outputs Source/Sink 24 mA • HD74ACT86 has TTL-Compatible Inputs Pin Arrangement 1 14 VCC 2 13 3 12 4 11 5 10 6 9 GND 7 8 Top view DC Characteristics (unless otherwise specified) Item Symbol

HD74AC139

Abstract: HD74ACT139 Hitachi DSA00348
Contextual Info: HD74AC139/HD74ACT139 Dual 1-of-4 Decoder/Demultiplexer Description The HD74AC139/HD74ACT139 is a high-speed, dual 1-of-4 decoder/demultiplexer. The device has two independent decoders, each accepting two inputs and providing four mutually-exclusive active-Low

Contextual Info: HD74AC158/HD74ACT158 D escription • Quad 2-Input Multiplexer Pin Assignment The H D 74A C 158/H D 74A C T158 is a high-speed quad 2-input m ultiplexer. It selects four bits of data from tw o sources using th e com m on Select and Enable inputs. T he four buffered o u tp u ts present

ow C541

Abstract: C541
Contextual Info: H D74AC540/H D74ACT540 HD74AC541 /HD74ACT541 •ffiSffi'.Ä?'"' Description The H D 74A C540/H D 74A CT540 and H D 74A C541/ H D 74ACT541 are octal buffer/line drivers designed to be em ployed as memory and address drivers, clock drivers and bus oriented transmitter/receivers.

004II

Contextual Info: H D 7 4 A C 1 0 9 / H D 7 4 A C T 1 0 9 *r;“ho„Po’ ”Ed°”T,s»«*d Description The HD74AC109/HD74ACT109 consists of two high­ speed completely independent transition clocked JK flipflops. The clocking operaiton is independent of rise and fall times of the clock waveform. The JK design allows

Contextual Info: HD74AC00/HD74ACT00 • Quad 2-Input NAND Gate >O u tp u ts Source/Sink 24 mA >H D 74A CT00 has TTL-C om patible Inputs Pin Assignment g n d T (T op View DC Characteristics (unless otherwise specified) P a r a m e te r Sym bol Ice Icc M ax M a x im u m Q u ie s c e n t

HD74ACT670

Abstract: PD245
Contextual Info: H D 7 4 A C 6 7 0 /H D 7 4 A C T 6 7 0 *i£i S S « Description Pin Assignment The HD74AC670/HD74ACT670 contains 16 high speed, low power, transparent D-type latches arranged as four words o f four bits each, to function as a 4 x 4 register file. Separate read and write

74AC194

Contextual Info: HD74AC194/HD74ACT194 Description Pin Assignment T h is b id ire ctio n al shift register is designed to in co rp o ra te v irtu a lly all o f th e features a system designer m ay w ant in a shift register. It features p a ralle l inputs, p a ralle l outputs,

74AC181

Abstract: 74ACT181 004II 225si HD74AC181
Contextual Info: HD74AC181/HD74ACT181 Description Pin Assignment I-1-S ./ The H D 74A C 181/H D 74A C T181 is a 4-bit A rith­ m etic logic U nit ALU w hich can perform all the possible 16 logic operations on tw o variables and a variety o f arithm etic operations. • O u tputs Source/Sink 24 mA

HD74AC86

Abstract: HD74AC86FPEL HD74AC86RPEL HD74ACT86
Contextual Info: HD74AC86/HD74ACT86 Quad 2-Input Exclusive-OR-Gate REJ03D0278–0200Z Previous ADE-205-362 (Z Rev.2.00 Jul.16.2004 Features • Outputs Source/Sink 24 mA • HD74ACT86 has TTL-Compatible Inputs • Ordering Information: Ex. HD74AC86 Part Name Package Type

Contextual Info: HD74AC86/HD74ACT86 • Quad 2-Input Exclusive-OR-Gate • Outputs Source/Sink 24 mA • HD74ACT86 has TTL-Compatible Inputs Pin Assignment Top View DC Characteristics(unless otherwise specified) Symbol Parameter Max Unit lee Maximum Quiescent Supply Current

Contextual Info: H D 7 4 A C 3 6 7 /H D 7 4 A C T 3 6 7 ‘a a s s s j. • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • Outputs Source/Sink 24 mA • HD74ACT367 has TTL-Compatible Inputs Pin Assignment Logic Sym bol Top View Pin Names U E i , OE2 3-State Output: Enable Input (Active

Contextual Info: H D 74A C 86/H D 74A C T86 • Output* Source/Sink 24 mA • HD74ACT86 has TTL-Comp*tible Inputs • Quad 2-Input Exclusive-OR-Gate Pin Assignment Top View D C Characteristics(unless otherwise specified) Symbo! P aram eter M ax Unit le t M aximum Quiescent

HD74AC154

Contextual Info: HD74AC154/HD74ACT154 Description The HD74AC154/HD74ACT154 is a multipurpose decoder designed to accept four inputs and provide 16 mutually exclusive outputs. By means of the Address Ao—A3 inputs, data applied to one of the Enable inputs can be routed to any one of the

Contextual Info: H D 7 4 A C 1 3 3 /H D 7 4 A C T 1 3 8 .1 - o f - 8 Description The HD74AC138/HD74ACT138 is a high-speed l-of-8 decoder/demultipiexer. This device is ideal!y suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow

CT365

Abstract: 74ac365
Contextual Info: HD74AC365/HD74ACT365'^'^°o&* • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • Output* Source/Sink 24 mA • HD74ACT366 has TTL-Compatible Inputs Pin Assignment 151 Vcc ISJöc HI1 SJo Logic Symbol OE, OEj IÖ i iDo SQi S o Top View

DECODER

Abstract: HD74AC138 HD74ACT138 Hitachi DSA00395
Contextual Info: HD74AC138/HD74ACT138 1-of-8 Decoder/Demultiplexer Description The HD74AC138/HD74ACT138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow

HD74ACT138FP

Abstract: HM628128 HM66205L CSA-012
Contextual Info: HM66205L Series 524,288-word x 8-bit High Density CMOS Static RAM Module Rev. 0.0 Dec. 1, 1995 Description The HM66205L is a high density 4-Mbit static RAM module which consists of 4 pieces HM628128BLT products TSOP type 1M static RAM and a HD74ACT138FP equivalent product (SOP type CMOS

HD74AC241

Abstract: HD74ACT241 Hitachi DSA00385
Contextual Info: HD74AC241/HD74ACT241 Octal Buffer/Line Driver with 3-State Output Description The HD74AC241/HD74ACT241 is an octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus-oriented transmitter or receiver which provides improved PC board

HD74AC366

Abstract: HD74ACT366 Hitachi DSA00395
Contextual Info: HD74AC366/HD74ACT366 Hex Inverter Buffer with 3-State Output Features • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • Outputs Source/Sink 24 mA • HD74ACT366 has TTL-Compatible Inputs Pin Arrangement OE1 1 16 VCC I 2 15 OE2 O 3