IC 74 138 DECODER Search Results

64LS138

Contextual Info: S N 5 4 LS 13 8 , SN 54S138, S N 74 LS 13 8 , S N 74 S 13 8 A 3-LINE TO 8-LINE D EC OD ERS/DEM U LTIPLEXERS DECEMBER 1972 —REVISED MARCH 1988 Designed Specifically for High-Speed: Memory Decoders Data Transmission Systems I I 3 Enable Inputs to Simplify Cascading

M02S7S7

Contextual Info: GD54/74LS138 3-TO-8-LINE DECODERS/DEMULTIPLEXERS Feature Pin Configuration • Designed Specifically for High Speed Memory Decoders and Data Transmission Systems • Incorporate 3 Enable Inputs to Simplify Cascading AND/OR Data Reception • Schottky Clamped for High Performance

Contextual Info: GD54/74LS138 3-TO-8-LINE DECODERS/DEMULTIPLEXERS Feature Pin Configuration • • • Designed Specifically for High Speed Memory Decoders and Data Transmission Systems Incorporate 3 Enable Inputs to Simplify Cascading AND/OR Data Reception Schottky Clamped for High Performance

74LS138PC

Abstract: 74LS138P 54S138DM 74S138PC demultiplexer 3 to 8 truth table 74LS138 connection for 74LS138 demultiplexer 74ls 74S138DC 74S138
Contextual Info: 138 C O N N E C T IO N D IA G R A M P IN O U T A 54S/74S138 ^ r 54LS/74LS138 &I&C n G c-s> Ao 1-OF-8 DECODER/DEMULTIPLEXER • • • • S C H O T T K Y P R O C E SS FO R H IG H SPEED D E M U L T IP L E X IN G C A P A B ILIT Y M U LT IP L E IN P U T ENABLE FO R EASY EXPANSIO N

block diagram of 74LS138 3 to 8 decoder

Abstract: block diagram of 74LS138 1 line to 16 line TTL 74ls138 74LS138 74LS138 3 to 8 74LS138 application note 74LS138 pin configuration 74LS138 3 to 8 decoder Pin of 74LS138 3 to 8 decoder 74ls138 3-8
Contextual Info: GD54/74LS138 3-TO-8-LINE DECODERS/DEMULTIPLEXERS Feature • Pin Configuration • D esigned Specifically for High S p e e d M em ory D ec o d e rs and Data Transm ission System s Incorporate 3 Enable Inputs to Simplify Cascading • A N D /O R Data R eception

74AHC138

Abstract: 74AHC138D 74AHC138PW 74AHCT138 74AHCT138D 74AHCT138PW TTL Schmitt-Trigger LOW POWER SCHOTTKY
Contextual Info: P hilips S em ico n d uctors Product sp ecification 74AHC138; 74AHCT138 3-to-8 line decoder/demultiplexer; inverting FEA TUR ES D ES C R IPTIO N • ESD protection: H BM E IA /JE S D 22-A 114-A E xceeds 2 0 0 0 V MM E IA /JE S D 22-A 115-A E xceeds 200 V The 74A H C /A H C T 138 are high-speed S i-gate C M O S devices and are pin

74AC138

Abstract: 74AC138M 74AC138DC sg81
Contextual Info: rZ m 7 Z S G S - T H O M S O N # I R a n e i ^ E I L l S 6 T [ s i © l D l g g _ 7 4 A C 1 3 8 _3 TO 8 LINE DECODER INVERTING . . HIGH SPEED: tPD =4.5 ns(TYP.) at Vcc = 5V LOW POWER DISSIPATION: Ic c = 8 |aA (MAX.) at T a = 25 °C

ic 74 LS 138 DECODER

Abstract: C455B
Contextual Info: U T 5 4 A C S 1 3 8 / U T 5 4 A C T S 13 8 Radiation-Hardened 3-Line to 8-Line Decoders/Demultiplexers PINOUTS FEATURES 16-Pin D IP Top View • 1.2 1 radiation-hardened CMOS - Latchup immune • High speed • Low power consumption • Single 5 volt supply

5 to 32 decoder using 4 t0 16 decoders

Abstract: LSI38 sn54138 LS138 SN54LS138 SN54S138 SN74LS138 SN74S138A
Contextual Info: SN54LS138, SN54S138, SN74LS138, SN74S13BA 3-LINE TO 8 LINE DECODERS/DEMULTIPLEXERS SDLS014 DECEMBER T9 7 2 — REVISED M A R C H 198 8 • Designed Specifically for High-Speed: Memory Decoders Data Transmission Systems • 3 Enable Inputs to Simplify Cascading

CI 74LS138

Abstract: 74LS138 pin configuration TTL 74ls138 74ls138 function 74 LS 138 DECODER intel 3205 74ls138 74l5138 of 74LS138 3 to 8 decoder 74LS138 ttl
Contextual Info: Signelics 74LS138, S138 Decoders/Demultiplexers 1 -O f - 8 D e c o d e r /D e m u ltip le x e r Product Specification L o g ic P ro d u c ts FEATURES • Demultiplexing capability • Multiple input enable fo r easy expansion TYPE 74LS138 74S138 • Ideal fo r m em ory chip select

ic 74 LS 138 DECODER

Abstract: IC 74ls138 74LS138 3 to 8 decoder notes 74LS138 1 to 8 decoder notes ic 74 138 DECODER
Contextual Info: g M OTOROLA SN 5 4 /7 4 L S 1 3 8 D E S C R IP T IO N — The L S T T L /M S IS N 5 4 L S /7 4 L S 1 38 is a high speed 1 -of-8 D ecoder/D em ultiplexer. This device is ideally suited for high speed bipolar m em ory ch ip select address decoding. The m ultiple input

Contextual Info: XC4000A Logic Cell Array Family Product Specifications Features Description • Third Generation Field-Programmable Gate Arrays - Abundant flip-flops - Flexible function generators - On-chip ultra-fast RAM - Dedicated high-speed carry-propagation circuit - Wide edge decoders two per edge

u18 328

Contextual Info: XC4000 Logic Cell Array Family Product Specifications Features Description • Third Generation Field-Programmable Gate Arrays - Abundant flip-flops - Flexible function generators - On-chip ultra-fast RAM - Dedicated high-speed carry-propagation circuit - Wide edge decoders four per edge

Contextual Info: r z T S G S -T H O M S O N ^ 7 # Kaneisi 5 iiLiCTifiì m6i_ 74A C 138 _ 3 TO 8 LINE DECODER (INVERTING) . HIGH SPEED: Ip d =4.5 ns(TYP.) at Vcc = 5V • LOW POWER DISSIPATION: Ic c = 8 |iA (MAX.) at Ta = 25 °C . HIGH NOISE IMMUNITY:

SN54138

Abstract: SN74LS138 LS138 SN54LS138 SN54S138 SN74S138A gl 1151
Contextual Info: SN54LS138, SN54S138, SN74LS138, SN74S138A 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS D E C E M B E R 1972 — R E V IS E D M A R C H 1988 Designed Specifically for High-Speed: Memory Decoders Data Transmission Systems S N 54LS 138, S N 54S 138 SN 74LS 138, S N 74S 138A

6251-10

Abstract: xatl 18VDDP LC897
Contextual Info: Ordering number : ENN6251 CMOS IC LC897127K SCSI CD-ROM Decoder with On-Chip DVD Interface Overview Package Dimensions unit: mm 3214-SQFP144 [LC897127K] 0.5 1.25 22.0 20.0 0.145 1.25 73 108 109 72 1.25 The LC897127K is a CD-ROM decoder that includes an on-chip DVD interface. Since the LC897127K also

Contextual Info: FAST CM OS 1-OF-8 D E CO DER WITH EN ABLE IDT54/74FCT1 38T/AT/CT FEATURES: DESCRIPTION: • • • • T he ID T 5 4 /7 4 F C T 13 8 T /A T /C T are 1-of-8 decoders built using an advanced dual metal C M O S tech n olo gy. The ID T 5 4/ 7 4 F C T 1 3 8 T /A T /C T accepts three binary weighted inputs Ao,

LOGIC OF 74LS138

Abstract: pin for 74LS138 74LS138 3 to 8 decoder notes 74LS138 74LS138 pins 74l5138 of 74LS138 3 to 8 decoder 74ls138 function TTL 74ls138 74LS138 3 to 8 decoder Pin
Contextual Info: 74LS138, S138 Signetics Decoders/Dem ultiplexers 1-Of-8 D e co d e r/D e m u ltip le xe r Product Specification L o g ic P rod ucts FEATURES • Demultiplexing capability • Multiple input enable for easy expansion • Ideal for memory chip select decoding

238D

Abstract: 138D 238C A7c DIODE
Contextual Info: ¡JCONOUCTOR Q U A LITY High Speed CMOS 1-of-8 Decoders Q UNO, Q S 54/74F C T 138 Q S 54 /7 4F C T 23 8 FEATURES/BENEFITS • QSFCT138D with 4.0ns prop, delay • lol-48 mA COM, 32 mA MIL • TTL-compatible input and output levels • Mil product compliant with MIL-STD 883, Class B

MC74ACT138

Contextual Info: M M O T O R O L A M C 74A C 138 M C 74A C T138 1 -of-8 D eco d er/D em u ltip lexer T h e M C 74 A C 1 38 /7 4 A C T 1 38 is a high-speed 1-of-8 d ecoder/dem ultiplexer. This device is ideally suited fo r high-speed bipolar m em ory chip select a ddress decoding.

FUNCTIONAL APPLICATION OF 74LS138

Abstract: 74LS138 3 to 8 decoder Pin of 74LS138 3 to 8 decoder 74LS138 3 to 8 decoder notes 74LS138 pin diagram 74LS138 74ls138 function pin for 74LS138 LOGIC DESCRIPTION OF 74LS138 74LS138 application note
Contextual Info: A m 2 5 L S 13 8 • A m 5 4 LS/7 4 L S 1 3 8 3-Line To 8-Line Decoder/Demultiplexer D IS T IN C T IV E C H A R A C T E R IS T IC S L O G IC D IA G R A M • • In v e rtin g and n o n -in v e rtin g enable inputs A m 2 5 L S devices o ffe r the fo llo w in g im p ro ve m e n ts over

MEK6802D3

Abstract: MT8964 MT8981D MT8981DC MT8981DE MT8981DL MT8981DP
Contextual Info: ISO-CMOS ST-BUS FAMILY  MT8981D Digital Switch Features ISSUE 6 May 1995 Ordering Information • Mitel ST-BUS compatible • 4-line x 32-channel inputs • 4-line x 32-channel outputs • 128 ports non-blocking switch • Single power supply +5 V

Contextual Info: GD54/74HC138, GD54/74HCT138 3-TO-8 LINE DECODER/DEMULTIPLEXER G eneral D e s c rip tio n These devices are identical in pinout to the 5 4 /7 4 L S 1 38. Each device has 3 Binary select A, B, and C , and decodes A 3-Bit address to 1 -of-8 active-LOW outputs. This device features three chip

5 to 32 decoder

Abstract: 5 to 32 decoder circuit YN 1041 top 244 yn MNA370 Decoder 5 to 32 74AHC138 74AHC138D 74AHC138PW 74AHCT138
Contextual Info: INTEGRATED CIRCUITS DATA SHEET 74AHC138; 74AHCT138 3-to-8 line decoder/demultiplexer; inverting Product specification Supersedes data of 1999 Mar 31 File under Integrated Circuits, IC06 1999 Sep 27 Philips Semiconductors Product specification 74AHC138; 74AHCT138