I1024 Search Results

STR 11006

Abstract: sc11075
Contextual Info: / v 2400 BPS Modem Advanced Controller MAC SIERRA SEMICONDUCTOR 44-P IN PLCC PACKAGE □ D irect interface to S C I1024 or SC11006 single chip m odem □ Com plete "A T " com m and set in internal firm w are

Contextual Info: l a tt ic e sem ico nducto r 4bE D • SBAfalMI G Q D m m h BILAT p L S r 1016 ü lL a ttic e programmable Large Scale Integration T -Ÿ é /' Ÿ Û ' wu.»ir.q r j ^ ■ ä ü ä a a iü ä Feature Ÿ a • PROGRAMMABLE HIGH DENSITY LOGIC —• Member of Lattice's pLSI Family

Contextual Info: Lattice ispLSF 1024 in-system programmable Large Scale Integration Features Functional Block Diagram • In-system programmable HIGH DENSITY LOGIC — — — — — — Member of Lattice’s IspLSI Family Fully Compatible with Lattice's pLSI Family High Speed Global Interconnects

Contextual Info: APP S? Î993 pLSÌ 1024 Lattice programmable Large Scale Integration High-Density Programmable Logic Functional Block Diagram Features U • PROGRAMMABLE HIGH-DENSITY LOGIC — — — — — Member of Lattice’s pLSI Family High-Speed Global Interconnects

Contextual Info: «P° «S 199? 1032 pLSI Lattine V i &« I w W programmable Large Sea Scale Integration Features Functional Block Diagram • PROGRAMMABLE HIGH DENSITY LOGIC — — — — — Member of Lattice’s pLSI Family High Speed Global Interconnects 64 I/O Pins, Eight Dedicated Inputs

APPLE A6 CHIP

Abstract: cf325 W07 sot 23 C-492-5 SMD M05 sot23 C4977 cf406 p66 apple c5297 I342
Contextual Info: 8 6 7 PDF CSA CONTENTS IMG5 17" REV E 11/01/05 SYNC MASTER DATE PDF CSA CONTENTS TABLE_TABLEOFCONTENTS_HEAD 2 System Block Diagram FINO-DD 06/20/2005 TABLE_TABLEOFCONTENTS_ITEM 3 4 Power Block Diagram FINO-PC 06/20/2005 5 Table Items FINO-M23 08/26/2005 6

STG1700

Abstract: Pixel Magic 35 ims 1700 I1024
Contextual Info: SGS-THOMSON :i[i g » 5 * I S jj STG 1700 TRUE COLOR PALETTE-DAC WITH 16-BIT PIXEL PORT • Operation up to 135MHz ■ 2:1 multiplexing using internal PLL ■ Standard VGA and high color operation up to 110MHz ■ Synchronous PixMix switching between modes

Contextual Info: Tem ic U6239B Semiconductors 2.9 GHz PLL for SAT TV Tuner with Universal Bus Description The U6239B is a single-chip frequency synthesizer with bidirectional I2C bus control and unidirectional 3-wire bus control, developed for SAT TV-tuner and cable tuner

Contextual Info: GOLDSTAR TECHNOLOGY I N C / 47E D • 4D2fl?S7 GoldStar 00035^4 □ GST T -W -/3 -/5 GM231000 131,072 WORDS x 8 BIT NMOS MASK ROM Pin Configuration D escription The GM231000 high-performance Read Only Memory is organized as 131,072 words by eight bits an access time of 200/250 ns. It is desgined

AL048

Contextual Info: 4bE D LATTICE SEMICON DUC TOR iiiLattice m SaôbTMS 0001434 a B ILAT p L S r 1032 programmable Large Scale Integration _ Pft'-/Ÿ-OŸ •■■■■■ m mfn • PROGRAMMABLE HIGH DENSITY LOGIC I — fmax = 80 MHz Maximum Operating Frequency — tpd = 15 ns Propagation Delay

Contextual Info: LATTICE SEMICONDUCTOR 4bE D il a t t ir p mL a C l « l i I w • SBfibTHT OÜOlMûb S ■ LAT pLSr 1024 w program m able Large Scale Integration : : : : T - v é - z i- ô « ? — Functional Block? Diagram* ¿m □ • PROGRAMMABLE HIGH DENSITY LOGIC — Member of Lattice’s pLSI Family

M52777SP

Abstract: M54630P M38881M2 m59320 57704L M38173M6 SF15DXZ M34236 m37204m8 54630p
Contextual Info: REFERENCE LIST T ype Page 2 S A 1 115 2SA1235 2 SA1235A 149 2 SC2237 *★ 2SA1282 2SA1282A 103 2 S C 5 1 25 149 2 S C 5 1 68 150 2 SC2320 150 2 SC 2320L 149 2 SC2538 2SA1283 2SA1284 2SA1285 149 2S C 2 6 03 149 2S C 2 6 27 2SA1285A 149 2 SC2628 2SA1286 153 AS 30

Contextual Info: p L S r 1024 Lattice programmable Large Scale Integration Functional Block Diagram Features • PROGRAMMABLE HIGH DENSITY LOGIC — Member of Lattice’s pLSI Family — High Speed Global Interconnects — 48 I/O Pins, Six Dedicated Inputs — 144 Registers

Contextual Info: M65KG256AF 256Mbit 4 Banks x 4M x 16 1.8 V Supply, 133MHz, DDR Low Power SDRAM Preliminary Data Feature summary • 256Mbit Synchronous Dynamic RAM – Organized as 4 Banks of 4MWords, each 16 bits wide ■ Double Data Rate (DDR) – 2 Data Transfers/clock cycle

IDT72225L25

Abstract: idt72215l50
Contextual Info: Integrated Device Technology, Inc. PRELIMINARY IDT72215A IDT72225A CMOS PARALLEL SyncFlFO CLOCKED FIFO 512 x 18-BIT & 1024 x 18-BIT FEATURES: DESCRIPTION: • • • • The IDT72215A and IDT72225A are very high speed, lowpowerfirst-in, first-out (FI FO) memories with clocked read and

intel 8096

Abstract: mc9346n STR 11006 S3175-2 SC11074 1022CN SC11054 SC11022CV SC11020CV N102H
Contextual Info: < ''> 2400 BPS Modem Advanced Controller MAC SIERRA SEMICONDUCTOR 44- & 68-PIN P L C C P A C K A G E S □ D irect interface to S C I 1024 or S C I 1006 single chip m odem □ Com plete "A T " com m and set in

Contextual Info: Lattice' ispLSI9 and pLSr 1024 | Semiconductor I Corporation High-Density Programmable Logic Functional Block Diagram Features □ HIGH-DENSITY PROGRAMMABLE LOGIC — — — — — High-Speed Global Interconnect 4000 PLD Gates 48 I/O Pins, Six Dedicated Inputs

Contextual Info: pLSr 1032 Lattice programmable Large Scale Integration Functional Block Diagram Features • PROGRAMMABLE HIGH DENSITY LOGIC — — — — — Member of Lattice’s pLSI Family High Speed Global Interconnects 64 I/O Pins, Eight Dedicated Inputs 192 Registers

SC1129

Abstract: SC11095 SC11270 SC11204
Contextual Info: SIERRA SEMI CONDUCTOR CORP M7E D • Ö24S01D OOOGTVS 7 ■ SSC FU N CTIO N A L INDEX—Data Com m unication Pro d u cts T*75*3& *^0 TYPE OF PRODUCT PRODUCT N U M BER 300 bps Modems SC11002CN /CM Bell 103 Com patible +5 Volts 15 SC11003CN /CM Sam e as SC11002, 5 Volt Only

Contextual Info: V SIERRA SEMICONDUCTOR SCU024 2400 Bit Per Second Modem Analog Peripheral The I1024 is a complete 2400 bps5 V only modem IC containing all modem functions except the adaptive equal­ izer. It is used in conjunction with an external controller, such as the Sierra

SI-10243

Contextual Info: lOOOpFj 2 K V 1 ! 1 PB 75 -A A /V 1 ! 1 75 ÎP2) -AA/V- ELECTRICAL SPECIFICATIONS: NDTES 1.0 TU R N S RATIO : ( P 6 - P 5 - P4 ( P 3 - P 2 - P1 J 6 -J 3 J 2 -J 1 2.0 INDUCTANCE: 3.0 LEAKAGE INDUCTANCE: 4.0 INTERWINDING CAPACITANCE: 5.0 DC RESISTANCE: ( J 6 - J 3 ) = (J 2 -J 1 )

IRLM2402

Abstract: c4977 cf325 NEC c5292 VD357 C5292 nec NEC "C4305" cf406 C4934 C5248
Contextual Info: 8 6 7 2 3 4 5 CK APPD FINO M23 1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. 1 REV ZONE ECN ENG APPD DESCRIPTION OF CHANGE DATE 19 397409 ENGINEERING RELEASED

Lattice PDS Version 3.0 users guide

Abstract: Latice 3Y1S 5-30-T 530t
Contextual Info: LATTICE SEMICONDUCTOR 4bE D H S3öbRMt1 QOOlSöfi 2 E3UÂT ispLSI 1024 in-system programmable Large Scale Integration •r-Ÿé-/?-07 □ • in-system programmable HIGH DENSITY LOGIC — Member of Lattice's IspLSI Family •— Fully Compatible with Lattice's pLSI Family

STR 11006

Abstract: MCS SERIAL IQR 336 NYP-196-18 SU UNI 30 ABV
Contextual Info: 2400 BPS Modem Advanced Controller MAC SIERRA SEMICONDUCTOR □ □ □ □ □ 4 8 -P IN D IP PA CK A G E D irect interface to SCI 1024 or SC 11006 single chip m odem C om plete "A T " com m and set