I0I1 Search Results

Contextual Info: 1 2 3 niM I 4 a MYLAR OPTION n l fn 1M 0.40 n f l rm m / M w w M m w w 1 0 0 0 0 0 ol ^ 1 01 01 10 10 0g I0I1I 0l 0l 0l 0l 0l 0l 0l 0g 0g0 0l 0l 1l 0l 0l 1 1 1 1 1 1 -B -tj-•—h-B Y- — id-B—+—B- El B

Contextual Info: TIB82S167BM , TIB82S167BC 1 4 x 4 8 x 6 FIELD PROGRAM M ABLE LOGIC SEQUENCER WITH 3 STATE OUTPUTS OR PRESET D2896, JANUARY 198b-REVISED DECEMBER 1987 Programmable Asynchronous Preset or Output Control M SU FFIX . . . J T PACKAGE C SUFFIX . . . J T OR N T PACKAGE

Contextual Info: Standard Products UT54ACTQ16374 RadHard CMOS 16-bit D Flip-Flop TTL Inputs, and Three-State Outputs Preliminary Datasheet November 2006 www.aeroflex.com/radhard LOGIC SYMBOL ‰ 16 non-inverting D flip-flops with three-state outputs ‰ Guaranteed simultaneously switching noise level and dynamic threshold performance

Contextual Info: Standard Products UT54ACTQ16374 RadHard CMOS 16-bit D Flip-Flop TTL Inputs, and Three-State Outputs Preliminary Datasheet November 2006 www.aeroflex.com/radhard LOGIC SYMBOL FEATURES ‰ 16 non-inverting D flip-flops with three-state outputs ‰ Guaranteed simultaneously switching noise level and dynamic threshold performance

Contextual Info: Standard Products UT54ACTQ16374 RadHard CMOS 16-bit D Flip-Flop TTL Inputs, and Three-State Outputs Advanced Datasheet September 13, 2006 www.aeroflex.com/radhard FEATURES LOGIC SYMBOL OE1 ‰ 0.6µm Commercial RadHardTM CMOS - Total dose: 100K rad Si - Single Event Latchup immune

Contextual Info: FINAL COM’L :-12/15/20 IND: -18/24 MACH LV210-12/15/20 Lattice/Vantis High Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • Low-voltage operation, 3.3-V JEDEC compatible — V c c = +3.0 V to +3.6 V ■ 83.3 MHz fcNT ■ 38 Bus-Friendly Inputs

STR W 5453 A

Abstract: STR W 5453 AX07CF192 AX07CF192-100 I6I15 ARM processor based Circuit Diagram splitter circuit
Contextual Info: AX07CF192 32-Bit Embedded Flash MCU User’s Manual Preliminary Aeroflex Microelectronic Solutions 4350 Centennial Blvd. Colo. Spgs., CO 80907 www.aeroflex.com January, 2003 Aeroflex Microelectronic Solutions Sales Offices Main Office 4350 Centennial Blvd.

CoolRunner

Abstract: memory device sense amplifier
Contextual Info: Fast Zero Power Traditional CPLDs • CPLDs migrated from Bipolar to CMOS – Easier platform to design upon – Lower power consumption – Continued to use the same Bipolar design technique to implement Product Terms • Product Term Construction Sense Amplifier

mach 3 family amd

Abstract: circuit diagram of QS 8005 PAL26V16 D750 MACH110 MACH210 MACH215 PAL22V10 mach 1 family amd NS4N
Contextual Info: FINAL COM’L: -7.5/10/12/15/20 IND: -10/12/14/18/24 M A C H 2 1 1 -7 / 1 0 / 1 2 / 1 5 /2 0 High-Density EE CMOS Programmable Logic Z I Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 44 Pins ■ 64 Macrocells ■ Programmable power-down mode ■ 32 Outputs

UT54ACTQ16374

Contextual Info: Standard Products UT54ACTQ16374 RadHard CMOS 16-bit D Flip-Flop TTL Inputs, and Three-State Outputs Datasheet March 20, 2007 www.aeroflex.com/radhard PIN DESCRIPTION FEATURES ‰ 16 non-inverting D flip-flops with three-state outputs ‰ Guaranteed simultaneously switching noise level and dynamic threshold performance

Contextual Info: PRELIMINARY DATA SHEET NEC MOS INTEGRATED CIRCUIT M PD4516421,4516821,4516161 16M bit Synchronous DRAM Description The UPD4516421, UPD4516821, uPD 4516161 are high-speed 16 777 2 1 6-bit synchronous dynamic random-access memories, each organized as 2 097 152-word x

HP3070

Abstract: PALCE22V10
Contextual Info: 1 FINAL MACH 1 & 2 FAMILIES COM’L: -5/7/10/12/15 IND: -7/10/12/14/18 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ◆ 44 Pins in PLCC and TQFP ◆ 32 Macrocells ◆ 5 ns tPD Commercial, 7.5 ns tPD Industrial ◆ 182 MHz fCNT ◆ 32 I/Os; 4 dedicated inputs/clocks; 2 dedicated inputs

kyx 28

Abstract: hstm 421 mrf 458 MRF 530 sharc ADSP-21xxx architecture A-18 ADSP-21160 matching smit chart diode LT 675 IN 407 ADSP-21106
Contextual Info: ADSP-21160 SHARC DSP Hardware Reference Revision 4.0, June 2009 Part Number 82-001966-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information 2009 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent

la 315

Abstract: mp 1038 FY yx 805 led driver A-18 ADSP-21160 a107 pa he nw diode lt 205 sharc 21xxx reference manual compiler book national semiconductor SBG LED MODUL
Contextual Info: ADSP-21160 SHARC DSP Hardware Reference Revision 3.0, November 2003 Part Number 82-001966-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information 2003 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent

MTS2916A

Contextual Info: MTS2916A Dual Full-Bridge Motor Driver Features Description • • • • • • • • • The MTS2916A motor driver is a CMOS device capable of driving both windings of a bipolar stepper motor or bidirectionally control two DC motors. Each of the two independent H-bridge outputs is capable of

Contextual Info: MTS62C19A Dual Full-Bridge Motor Driver Features Description • • • • • • • • • The MTS62C19A motor driver is a CMOS device capable of driving both windings of a bipolar stepper motor or bidirectionally control two DC motors. Each of the two independent H-bridge outputs is capable of sustaining 40V and delivering up to 750 mA of continuous

PD48

Abstract: uPD481850GF-A12-JBT
Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD481850 8M-bit Synchronous GRAM Description The µPD481850 is a synchronous graphics memory SGRAM organized as 128 K words x 32 bits × 2 banks random access port. This device can operate up to 100 MHz by using synchronous interface. Also, it has 8-column Block Write

uPD481850

Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD481850 8 M-bit Synchronous GRAM for Rev.L Description The µPD481850 is a synchronous graphics memory SGRAM organized as 131,072 words x 32 bits × 2 banks random access port. This device can operate up to 100 MHz by using synchronous interface. Also, it has 8-column Block Write

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD4516421-PC, 4516821-PC, 4516161-PC 16M-bit Synchronous DRAM for PC SDRAM Lite Description The µPD4516421-PC, 4516821-PC, 4516161-PC are high-speed 16,777,216-bit synchronous dynamic randomaccess memories, organized as 2,097,152 x 4 × 2, 1,048,576 × 8 × 2 and 524,288 × 16 × 2 word × bit × bank ,

UPD4502161

Abstract: upd4502161g5a12 UPD4502161G5A12-7JF PD4502161 BD3/1/TX13/7.9/PP10/UPD4516421G5-A12-7JF
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD4502161 2M-bit Synchronous DRAM Description The µPD4502161 is a high-speed 2,097,152-bit synchronous dynamic random-access memory, organized as 65,536 x 16 × 2 word × bit × bank , respectively. The synchronous DRAM achieves high-speed data transfer using the pipeline architecture.

Contextual Info: F100164 16-Input Multiplexer F A IR C H IL D A Schlumberger Company F100K ECL Product Connection Diagrams Description The F100164 is a 16-input multiplexer. Data paths are controlled by four Select lines S 0 - S 3 •Their decoding is shown in the truth table. Output data polarity is the

SC100

Abstract: SC140 A3D instruction manual A2C 532 159 33
Contextual Info: MNSC100ABI/D Rev. 1.8, 4/2000 SC100 Application Binary Interface Reference Manual MNSC100ABI/D Rev. 1.8, 4/2000 SC100 Application Binary Interface Reference Manual This document contains information on a new product. Specifications and information herein are subject to change

Contextual Info: PRELIMINARY KM4216C258/L/F, KM4216V258/I-/F 256K 16 Bit CM OS Video RAM x FEATURES GENERAL DESCRIPTION Dual port Architecture 2S6K x 16 bits RAM port 512 x 16 bits SAM port Performance range: _ t-• —_ _ Speed Parameter — -RAM access tim e tRAC

MECL handbook

Abstract: AN726 MECL MC10123 AN-726 MC101 MC10110 MC10111
Contextual Info: AN-726 Application Note c BUSSING WITH MECL 10,000 INTEGRATED CIRCUITS Prepared by Bill Blood C o m p u te r A p p lic a tio n s High speed data bus lines are an im ­ p o rta n t p art o f m odern c o m p u ter systems. Features a llo w of the c o n s tru c tio n