HYB39 Search Results

Contextual Info: S IE M E N S HYB39S16160CT-6/-7 16MBit Synchronous DRAM 1M x 16 M Bit S yn ch ro n o u s DRAM fo r High S peed G raph ics A p p lication s • High Performance: full page optional around for sequencial wrap -6 -7 Units fCKm ax @ CL=3 166 143 MHz tCK3 6 7

HYB39SC128169EE-7

Abstract: HYB39SC128169EE
Contextual Info: October 2006 HYB39SC128169EE HYB39SC128329EE 128-MBit Synchronous DRAM Green Product SDRAM Internet Data Sheet Rev. 1.00 Internet Data Sheet HYB39SC128[16/32]9EE 128-MBit Synchronous DRAM Revision History: 2006-10, Rev. 1.0 All Adapted internet edition All

DMX RECEIVER

Abstract: HYB39 HYB39D32322TQ LQFP100 infineon sgram SGRAM
Contextual Info: Memories for Graphics Systems 32Mbit DDR SGRAM HYB39D32322TQ -6 -A2 Die revision A2 User’s Manual Version 2.12 06.2000 Edition 06.2000 This edition was realized using the software system FrameMaker. Published by Infineon Technologies, Marketing-Kommunikation,

Siemens SCR components Data Manual

Abstract: HYB39S16320TQ HYB39S16320TQ-6 HYB39S16320TQ-7 HYB39S16320TQ-8 SIEMENS BST t
Contextual Info: Memories for Graphics Systems 16M Synchronous Graphics RAM SGRAM HYB39S16320TQ-6 HYB39S16320TQ-7 HYB39S16320TQ-8 Version 2.1.00 Preliminary Information SGRAM 1.1999 HYB39S16320TQ-6/-7/-8 Revision History: Current Version 2.1.00 Previous Version: 1.x.xx Page

marking code EY SMD

Abstract: PC100-222-620 P-TSOPII-54
Contextual Info: HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 256 MBit Synchronous Low-Power DRAM Data Sheet Revision Dec. 2002 • Automatic and Controlled Precharge Command Features -7.5 -8 Units fCK,MAX 133 125 MHz • Programmable Burst Length: 1, 2, 4, 8 and full page tCK3,MIN

HYB39S256400FE-7

Abstract: HYI39S256160FE7 HYB39S256160FT-7 hyb39s256800fe HYB39S256800FE-7 HYB39S256400FF-7 HYB39S256407FE HYB39S256160 HYB39S256160FE HYI39S256160
Contextual Info: September 2007 HY[B/I]39S256[40/80/16]0FT L HY[B/I]39S256[40/80/16]0FE(L) HYB39S256[40/80/16]0FF(L) HYB39S 256407 F E 256-MBit Synchronous DRAM SDRAM Internet Data Sheet Rev. 1.42 Internet Data Sheet HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L) 256-MBit Synchronous DRAM

ISO 8015

Abstract: HYB39SC256 "ISO 8015" PC166-333 HYI39SC256160FE-6 Qimonda AG HYB
Contextual Info: June 2007 HYB39SC256[80/16]0FE HYI39SC256[80/16]0FF 256-MBit Synchronous DRAM Green Product SDRAM Internet Data Sheet Rev. 1.25 Internet Data Sheet HY[B/I]39SC256[80/16]0F[E/F] 256-MBit Synchronous DRAM HYB39SC256[80/16]0FE, HYI39SC256[80/16]0FF Revision History: 2007-06, Rev. 1.25

SEM t11

Abstract: 39S16800 39S16800AT-8 Q1323 q1333
Contextual Info: HYB39S1640x/80x/16xAT-8/-10 16MBit Synchronous DRAM SIEMENS 16 MBit Synchronous DRAM second generation Advanced Information • High Performance: Multiple Burst Operation CAS latency = 3 -8 -10 Units fCK 125 100 MHz tCK3 8 10 ns tAC3 7 8 ns Automatic Command

39S256160DT-7

Abstract: HYB39S256400D PC133-222-520 PC166
Contextual Info: Data Sheet, Rev. 1.02, Feb. 2004 HYB39S256400D[C/T] L HYB39S256800D[C/T](L) HYB39S256160D[C/T](L) 256-MBit Synchronous DRAM SDRAM Memory Products N e v e r s t o p t h i n k i n g . Edition 2004-02 Published by Infineon Technologies AG, St.-Martin-Strasse 53,

Contextual Info: HYB39S16160CT-6/-7 16MBit Synchronous DRAM 1M x 16 MBit Synchronous DRAM for High Speed Graphics Applications • High Performance: • full page optional for sequencial wrap around • Multiple Burst Read with Single Write Operation • Automatic Command

Contextual Info: September 2006 HYB39S C12880 0 FE HYB39S C12816 0 FE HYI39SC128800FE HYI39SC128160FE 128-MBit Synchronous DRAM Green Product SDRAM Internet Data Sheet Rev. 1.00 Internet Data Sheet HY[B/I]39SC128[800/160]FE 128-MBit Synchronous DRAM Revision History: Rev. 1.00, 2006-09

39S16802AT-10

Abstract: Q67100-Q1279 marking t8 smd CAY Q67100-Q1323 Q67100-Q1327 Q67100-Q1333 Q67100-Q1335 P-TSOPII-44 BX-4T
Contextual Info: HYB39S1640x/80x/16xAT-8/-10 16MBit Synchronous DRAM 16 MBit Synchronous DRAM second generation Advanced Information • High Performance: CAS latency = 3 -8 -10 Units fCK 125 100 MHz tCK3 8 10 ns tAC3 7 8 ns • Multiple Burst Read with Single Write Operation

active suspension

Contextual Info: HYB39S1640x/80x/16xAT 16MBit Synchronous DRAM Timing Diagrams 1. Bank Activate Command Cycle 2. Burst Read Operation 3. Read Interrupted by a Read 4. Read to Write Interval 4.1 Read to Write Interval 4.2 Minimum Read to Write Interval 4.3 Non-Minimum Read to Write Interval

Contextual Info: SIEMENS HYB39S64400/800/160AT L 64MBit Synchronous DRAM 64 MBit Synchronous DRAM • High Performance: Multiple Burst Operation -8 -8B -10 Units fCKmax. 125 100 100 MHz tCK3 8 10 10 ns tAC3 6 6 7 ns Automatic Command and Read with Single Write Controlled

P-TSOPII-54

Abstract: 39S64160BT-7 39S64160AT-5
Contextual Info: HYB39S64160A/BT-5.5/-6/-7 64MBit Synchronous DRAM 4M x 16 MBit Synchronous DRAM for High Speed Graphics Applications • High Performance: • full page optional for sequencial wrap around • Multiple Burst Read with Single Write Operation • Automatic

PC133-333

Abstract: P-TSOPII-54 hyb39s64400
Contextual Info: HYB39S64400/800/160A/BT L 64MBit Synchronous DRAM Ultra High Speed 64 MBit Synchronous DRAM PC143 & PC133 • High Performance: -7 -7.5 Units fCKmax. 143 133 MHz tCK3 7 7.5 ns tAC3 5.4 5.4 ns tCK2 10 10 ns tAC2 5.5 6 ns • Fully Synchronous to Positive Clock Edge

39S256160T

Abstract: PC100-322-620 smd CAY PC100-322 P-TSOPII-54
Contextual Info: HYB39S256400/800/160T 256MBit Synchronous DRAM 256 MBit Synchronous DRAM Preliminary Information • High Performance: -8 -8A -8B Units fCK 125 125 100 MHz tCK3 8 8 10 ns tAC3 6 6 6 ns tCK2 10 12 15 ns tAC2 6 6 7 ns • Fully Synchronous to Positive Clock Edge

PC133-222-520

Abstract: PC133-222 HYB39S256160FE-7 HYB39S256160FT-7 hyb39s256800fe P-TSOPII-54 HYB39S256160FE HYB39S256800FE-7 00FF TSOP-II-54
Contextual Info: September 2006 HYB39S256[4/8/16]00FT L HYB39S256[4/8/16]00FE(L) HYB39S256[4/8/16]00FF(L) 256-MBit Synchronous DRAM SDRAM Internet Data Sheet Rev. 1.21 Internet Data Sheet HYB39S256[400/800/160]F[E/T/F](L) 256-MBit Synchronous DRAM HYB39S256[4/8/16]00FT(L), HYB39S256[4/8/16]00FE(L), HYB39S256[4/8/16]00FF(L)

PQFP128

Abstract: HYB39M83200 HYB39M83200L HYB39M83200Q HYB39M93200 HYB39M93200L HYB39M93200Q PLCC68 PQFP-128 TQFP-100
Contextual Info: 288k x 32 / 256k x 32 M ULTIBANK DRAM M DRAM HYB39M93200 HYB39M83200 Preliminary Information * Ultra-High Performance 666 M B yte/sec single device transfer rate 36 ns RAS access 13.8 ns CAS access 6 ns burst cycle * Multibank Architecture RAS and precharge may overlap CAS READ or W R ITE to different banks effectively hiding

Contextual Info: March 2007 HYB39S128400F[E/T] L HY[B/I]39S128800F[E/T](L) HY[B/I]39S128160F[E/T](L) HYB39S 128407 F E 128-MBit Synchronous DRAM Green Product SDRAM Internet Data Sheet Rev. 1.3 Internet Data Sheet HY[B/I]39S128[40/80/16][0/7]F[E/T](L) 128-MBit Synchronous DRAM

HYB39S256160FE

Abstract: HYB39S256160FE-7
Contextual Info: March 2007 HY[B/I]39S256[40/80/16]0FT L HY[B/I]39S256[40/80/16]0FE(L) HYB39S256[40/80/16]0FF(L) HYB39S 256407 F E 256-MBit Synchronous DRAM SDRAM Internet Data Sheet Rev. 1.3 Internet Data Sheet HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L) 256-MBit Synchronous DRAM

Contextual Info: HYB39V64x0yT 64MBit Virtual Channel SDRAM SIEM ENS 64MBit Virtual Channel SDRAM 1 Advanced Information • • • • • • • • • • • • • • • • 1.1 Fully Standard Synchronous Dynamic RAM, with all signals referenced to a positive clock edge

P-TSOPII-54

Abstract: PC133 registered reference design
Contextual Info: HYB39S512400/800/160AT L 512MBit Synchronous DRAM 512 MBit Synchronous DRAM Preliminary Datasheet April ’01 • High Performance: -6 -7 -7.5 -8 Units fCK 166 143 133 125 MHz tCK3 6 7 7.5 8 ns tAC3 5 5.4 5.4 6 ns tCK2 7.5 7.5 10 10 ns tAC2 5.4 5.4 6 6 ns

39S256160DT-7

Abstract: HYB 39S256160DT-7.5 PC100-222 PC133-222 P-TSOPII-54 P-TSOP-54-2
Contextual Info: HYB39S256400/800/160DT L /DC(L) 256MBit Synchronous DRAM 256 MBit Synchronous DRAM • High Performance: -6 -7 -7.5 -8 Units • Data Mask for Read / Write control (x4, x8) • Data Mask for byte control (x16) • Auto Refresh (CBR) and Self Refresh fCK 166