HSSI PROTOCOL Search Results

hdlc

Abstract: CRC-32 PM4354 PM7364 PM7367 PM8315
Contextual Info: PMC-Sierra,Inc. PM7367 FREEDM-32P32 Preliminary 32 link, 32 Channel Data Link Manager with PCI Interface FEATURES • Supports a mix of channelized and unchannelized links. • The maximum aggregate clock rate is 64 MHz. When the device is interfaced to two T3 or HSSI links, the maximum

altera ethernet packet generator

Abstract: verification for pci express xaui xaui xgmii ip core altera transactor hssi protocol
Contextual Info: DesignCon 2007 Serial Protocol Compliance of an FPGA-Integrated Mixed-Signal Transceiver Divya Vijayaraghavan, Altera Corporation Ramanand Venkata, Arch Zaliznyak, Michael Zheng, Steven Shen, Binh Ton, Lana Chan, Steve Park, Chong Lee, Rakesh Patel, Richard Cliff,

infiniband Physical Medium Attachment

Abstract: "toan nguyen" 200MHZ P802 circuit diagram digital clocks Serial RapidIO Infiniband FPGA SoC, Chip, telecom fpga da altera altera 48 fpga 1gbps serdes
Contextual Info: Architecture and Methodology of a SoPC with 3.25Gbps CDR based Serdes and 1Gbps Dynamic Phase Alignment Ramanand Venkata, Wilson Wong, Tina Tran, Vinson Chan, Tim Hoang, Henry Lui, Binh Ton, Sergey Shumurayev, Chong Lee, Shoujun Wang, Huy Ngo, Malik Kabani, Victor Maruri, Tin Lai, Tam Nguyen, Arch

PRBS altera verilog

Abstract: mixed signal fpga datasheet papers ethernet mac verilog testbench altera ethernet packet generator SerialLite verification for pci express
Contextual Info: DesignCon 2006 Functional Verification of 622-Mbps–6.375-Gbps Transceiver IP in an FPGA Ning Xue, Altera Corporation [nxue@altera.com] Ramanand Venkata, Arch Zaliznyak, Divya Vijayaraghavan, Steve Park, Chong Lee, Rakesh Patel (Altera Corporation) CP-TRNSCVR-1.0

txc-03361 application notes

Abstract: 97029 MVIP-90 PM4351 PM6344 PM7366 PM8313 application notes txc-03361 e1 E2 e3 liu transceiver
Contextual Info: PM7366 FREEDM-8 APPLICATION NOTE PMC-971178 ISSUE 1 FRAME ENGINE AND DATA LINK MANAGER PM7366 FREEDM-8 ANSWERS TO FREQUENTLY ASKED QUESTIONS REGARDING THE FREEDM-8 ISSUE 1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

serial number of internet manager

Abstract: PMC-970931 PM6344 PM7366 CRC-32 PM4314 PM4388 PM4314QDSX
Contextual Info: PM7366 FREEDM-8 APPLICATION NOTE PMC-970931 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER PM7366 FREEDM-8 FRAME ENGINE AND DATA LINK MANAGER TECHNICAL OVERVIEW ISSUE 2: SEPTEMBER 1997 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

CRC-32

Abstract: PM7364
Contextual Info: PM7364 FREEDM-32 APPLICATION NOTE PMC-970932 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER PM7364 FREEDM-32 FRAME ENGINE AND DATA LINK MANAGER TECHNICAL OVERVIEW ISSUE 2: SEPTEMBER 1997 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

infineon SAB 82532

Abstract: DSCC4
Contextual Info: P R O D U C T B R I E F Multiprotocol DMA supported Serial Communication Controller with 4 Channels The DSCC4 PEB 20534 is a multiprotocol data communication controller with four symmetrical serial channels. The DSCC4 is offering two high speed channels. Data rates up to 52 Mbit/s are

Contextual Info: PM PM7366 FREEDM-8 PMC-Sierra,Inc. Frame Engine and Datalink Manager FEATURES High density HDLC controller ideal for Internet access, Frame Relay, and DSLAM equipment supporting rates ranging from 56 Kbit/s to 52 Mbit/s. Supports eight full-duplex and independently-timed links.

CRC-32

Abstract: PM7364 PM7366 4388
Contextual Info: TM PM7364 FREEDM Preliminary Information 32 FRAME ENGINE AND DATA LINK MANAGER FEATURES • High density HDLC controller ideal for Internet access, Frame Relay and DSLAM equipment supporting rates ranging from 56 Kbit/s to 52 Mbit/s. • Supports 32 full-duplex and

Contextual Info: PM7366 PMC-Sierra, Inc. Preliminary Information FEATURES High density HDLC controller ideal for The maximum aggregate clock rate is Supports scatter-gather capabilities Internet access, Frame Relay and DSLAM equipment supporting rates ranging from 56 Kbit/s to 52 Mbit/s.

hdlc

Abstract: CRC-32 PM4314 PM4388 PM6388 PM7346 PM7364 PM7366 quad channel relay board
Contextual Info: PM7366 FREEDM-8 PMC-Sierra,Inc. Frame Engine and Datalink Manager FEATURES • High density HDLC controller ideal for Internet access, Frame Relay, and DSLAM equipment supporting rates ranging from 56 Kbit/s to 52 Mbit/s. • Supports eight full-duplex and

24 port liu

Abstract: hdlc CRC-32 PM4314 PM4388 PM6388 PM7364 PM7366 PM8313 quad channel relay board
Contextual Info: PM7364 FREEDM-32 PMC-Sierra,Inc. Frame Engine and Datalink Manager FEATURES • High density HDLC controller ideal for Internet access, Frame Relay, and DSLAM equipment supporting rates ranging from 56 Kbit/s to 52 Mbit/s. • Supports 32 full-duplex and independently-timed links.

32 channel Relay controller IC

Abstract: CRC-32 PM7364 PM7366
Contextual Info: TM PM7366 FREEDM Preliminary Information 8 FRAME ENGINE AND DATA LINK MANAGER FEATURES • High density HDLC controller ideal for Internet access, Frame Relay and DSLAM equipment supporting rates ranging from 56 Kbit/s to 52 Mbit/s. • Supports 8 full-duplex and

BGP-4

Abstract: marking bgp CS03 ICES-003 TS001 X509V3 "L2TP" "BGP" "OSPF"
Contextual Info: Access Point 450 Multiservice IP Access Router Access Point 450 is a mid-range IP/Internet access router designed to deliver world-class IP services with the performance, security, and the Quality of Service control needed to build next generation IP/Internet

MSC8156

Abstract: SC3850 MSC8156 datasheet MSC8156ADS MSC8156EVM Transforms viterbi circuitry ifft
Contextual Info: Digital Signal Processors MSC8156 High-Performance Multicore DSP Six-core programmable DSP for medical imaging, aerospace, defense and advanced test and measurement Overview technology in a highly integrated SoC to protocols to guarantee reliable data transport

EP3C10

Abstract: EP3SE50 EP4SGX360 EP4SGX70 EPM240Z LVDS receiver 315MHZ DPA Labs
Contextual Info: Quartus II Device Support Release Notes July 2008 Quartus II version 8.0 SP1 This document provides late-breaking information about device support in this version of the Altera Quartus® II software. For information about memory, disk space, and system requirements, refer to the readme.txt file in your

SC3850

Contextual Info: Digital Signal Processors MSC8154 Broadband Wireless Access DSP Advanced 45 nm, four-core DSP for 3G-LTE, TDD-LTE, WiMAX, 3GPP-HSPA and TD-SCDMA Overview wireless standards such as 3G-LTE, WiMAX, supports multiple networking protocols The MSC8154 is a four-core DSP based on

Contextual Info: Clock Networks and PLLs in Stratix V Devices 4 2013.05.06 SV51005 Subscribe Feedback This chapter describes the advanced features of hierarchical clock networks and phase-locked loops PLLs in Stratix V devices. The Quartus® II software enables the PLLs and their features without external devices.

mini-lvds source driver

Abstract: ep4cgx110 JEDEC FBGA ttl to mini-lvds EP4CE115 EP4CE55 mini-lvds 4CGX150 148QFN 169-FBGA
Contextual Info: 6. I/O Features in Cyclone IV Devices CYIV-51006-2.1 This chapter describes the I/O and high speed I/O capabilities and features offered in Cyclone IV devices. The I/O capabilities of Cyclone IV devices are driven by the diversification of I/O standards in many low-cost applications, and the significant increase in required I/O

CLK12

Abstract: CLK21 SV51005-1
Contextual Info: 4. Clock Networks and PLLs in Stratix V Devices SV51005-1.0 This chapter describes the hierarchical clock networks and phase-locked loops PLLs which have advanced features in Stratix V devices. It includes information about reconfiguring the PLL counter, clock frequency, and phase shift in real time, which

EP3SE50F780

Abstract: EP3C10M164 EP3C40Q240 EP3SL110F1152 ep3se110f1152 EP3SL70F780 HC210 36x36-bit EP3SL150ES ep3se80f780
Contextual Info: Quartus II Device Support Release Notes May 2008 Quartus II version 8.0 This document provides late-breaking information about device support in this version of the Altera Quartus® II software. For information about memory, disk space, and system requirements, refer to the readme.txt file in your

NORTEL PASSPORT 8600

Abstract: bcn router bcn bln ag13 BLN 71000 NORTEL PASSPORT MSA cards NORTEL PASSPORT datasheet cards Nortel 8600 cable 13-Slot NEMA-5-15R
Contextual Info: PB3785-A.qxd 10/18/00 4:10 PM Page iii Product Brief Backbone Node Backbone Link Node/Concentrator Node Large networks require a high-performance, scalable routing device capable of delivering all types of data quickly and efficiently, over any network topology,

Contextual Info: Freescale Semiconductor Data Sheet Document Number: MSC8252 Rev. 8, 08/2013 MSC8252 Dual-Core Digital Signal Processor • Two StarCore SC3850 DSP subsystems, each with an SC3850 DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, unified 512 Kbyte L2 cache configurable as M2 memory in