TRANSACTOR Search Results

7256A

Abstract: 7256AE mt46v32m8 EP1S25F1020C5 EPM3256A PCI_T32 MegaCore Optrex vhdl code for ddr sdram controller altera board
Contextual Info: PCI Development Kit, Stratix Edition Getting Started User Guide 101 Innovation Drive San Jose, CA 95134 408 544-7000 www.altera.com UG-STXPCIDVKT-1.0 P25-09107-00 Kit Version: Document Version: Document Date: 1.0.0 1.0.0 rev. 1 May 2003 Copyright PCI Development Kit, Stratix Edition Getting Started User Guide

verilog code for amba ahb bus

Abstract: verilog code for amba ahb master excalibur Board
Contextual Info: Excalibur Bus Functional Model User Guide July 2002 Version 1.2 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com A-UG-XBUS-1.2 Excalibur Bus Functional Model User Guide Copyright  2002 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all

21064A-200

Abstract: 21064A-233 21064A-275 21064A-275-PC 21064A-300 pfn 109 06f irf 4110 M23VDD gh11
Contextual Info: Alpha 21064A Microprocessors Data Sheet Order Number: EC–QFGKC–TE This document contains information about the following Alpha microprocessors: 21064A–200, 21064A–233, 21064A–275, 21064A–275–PC, and 21064A–300. Revision/Update Information:

852 transistor datasheet

Abstract: analog devices select guide 2010 Master/Target PCI VHDL Core pci verilog code verilog hdl code for parity generator vhdl code for 8-bit parity checker PCI_T32 MegaCore Extended PCI Arbiter PCI PROJECT verilog code for pci to pci bridge
Contextual Info: PCI Compiler User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Compiler Version: Document Date: 10.0 July 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

UniPHY

Abstract: DDR3 model verilog codes
Contextual Info: Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com EMI_QDRII_UG-2.0 Document Version: Document Date: 2.0 July 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

AMBA ahb bus protocol

Abstract: verilog code for ahb bus slave ahb wrapper verilog code excalibur Board
Contextual Info: Excalibur Bus Functional Model User Guide July 2002 Version 1.2 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com UG-XBUS-1.2 Excalibur Bus Functional Model User Guide Copyright  2002 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all

avalon verilog

Abstract: vhdl code for branch metric unit vhdl code for traffic light control lanex branch metric unit VHDL design vhdl program for branch metric unit 8CRV
Contextual Info: DesignCon 2010 Functional Verification of Highly Parameterizable IP and SystemLevel Design-Assembly Tools for FPGAs Jeffrey R. Fox, Altera Corporation jfox@altera.com Kent Orthner, Altera Corporation korthner@altera.com CP-01062-1.0 January 2010 Abstract Advances in verification technology for digital design, such as SystemVerilog Testbench

A7721

Abstract: A7817 int1200 h30 tb15 A7801 IXP1200 a7737 a7741 a4772-01 A7747
Contextual Info: IXP1200 Network Processor Datasheet Product Features The IXP1200 Network Processor delivers high-performance processing power and flexibility to a wide variety of LAN and telecommunications products. Distinguishing features of the IXP1200 are the performance of ASIC hardware

BT8233EHFB

Abstract: 5969b l8233
Contextual Info: R O C K W E L L Network access S E M I C O N D U C T O R Bt8233 ATM ServiceSAR with S Y S T E M S xBR Traffic Management datasheet PROVIDING HIGH SPEED MULTIMEDIA CONNECTIONS September 1998 Bt8233 ATM ServiceSAR with xBR Traffic Management The Bt8233 Service Segmentation and Reassembly Controller integrates in a single

I960CA

Abstract: CRC10 RS8234 RS8250 on-demand multicast messages
Contextual Info: RS8234 ATM ServiceSAR Plus with xBR Traffic Management The RS8234 Service Segmentation and Reassembly Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA interface with service specific functions in a single package. The ServiceSAR Controller generates and

I960CA

Abstract: CN8236 CX28250EVM Bt8223
Contextual Info: CN8236 ATM ServiceSAR Plus with xBR Traffic Management The CN8236 Service Segmentation and Reassembly Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA level 1 or 2 interface with service-specific functions in a single package for AAL0, 3/4, and 5 operations.

Intel IXA SDK Developers Workbench

Abstract: ixp sdk IXF440 IXDP1200 IXF1002 IXM1200 IXP1200 IXP1200 Network Processor Family Microcode Program intel ixa sdk CJ22
Contextual Info: 10671H.qxd 5/11/01 1:57 PM Page 1 product brief Intel Internet Exchange Architecture Software Developers Kit 2.0 for the IXP1200 Network Processor Software for a Total Development Environment Enabling Next-Generation Networks Product Highlights Intel Internet Exchange

IDT75K134SLM

Abstract: IXP2400 IXP2800 microengine intel ixa sdk
Contextual Info: IDT LA-1 NSE System Level Architecture Model for Intel IXA SDK Microengine Development Environment Features List Introduction Evolving network speeds require critical functions, such as forwarding and classification, to migrate towards dedicated hardware devices. IDT

siemens rs1002A

Abstract: RS1002A YL-1050 RS1072C siemens rs 1002A Q81-X1410 kg391 siemens triode yl1010 siemens datenbuch
Contextual Info: SIEMENS Datenbuch 1976/77 I Senderöhren In h a lts v e rz e ic h n is A u s w a h lta b e lle Ä q u iv a le n te R ö h re n ty p e n S y m b o lv e rz e ic h n is E rlä u te ru n g e n zu d en te c h n is c h e n D a te n D a te n b lä tte r RS 5 23 bis RS 1082 C

Contextual Info: RS8235 Endstation ATM ServiceSAR with xBR Traffic Management The RS8235 Service Segmentation and Reassembly Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA interface with service specific functions in a single package. The ServiceSAR Controller generates and

IXF6012

Abstract: IXP1200 IXP1240 64Kentry
Contextual Info: IXP12xx ATM OC12/Ethernet IP Router Example Design Performance and Headroom Analysis April, 2002 Document Number: 301144-001 Version 1.0, 4/10/02 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or

router board 433 circuit diagram for ethernet

Abstract: fastpath router ixp1240 microengine CRC-32 IXP1200 IXP1250
Contextual Info: IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Application Note - Rev 1.0, 3/20/2002 Order Number: 278393-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

Marvell 88E1111 vhdl

Abstract: marvell 88e1145 88E1111 PHY registers map Triple-Speed Ethernet M DM7041 Marvell PHY 88E1111 finisar 5SGXM DP83865 88E1111 stratix iii MDIO clause 22 5SGXMA 88E1145 registers
Contextual Info: Triple-Speed Ethernet MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Date: 11.1 November 2011 Copyright 2011 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

secret

Abstract: DS1961S DS1963S DS2432 electronic tokens
Contextual Info: White Paper 4 Glossary of 1-Wire SHA-1 Terms www.maxim-ic.com INTRODUCTION This document contains a list of terms pertaining to the use of 1-Wire SHA-1 devices such as the DS1963S, DS1961S, and DS2432. Every effort is being made to make the terms in the various

CN8237EBGB

Abstract: CX29704 RS8234 RS8235 PCI x1 express PCB dimensions artwork BC 5473
Contextual Info: CN8237 ATM OC-12 ServiceSAR Plus with xBR Traffic Management The CN8237 Service Segmentation and Reassembly ServiceSAR Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA 1 or 2 interface with service-specific functions in a single package for AAL0 and AAL5 operations. The ServiceSAR

Contextual Info: RS8235 Endstation ATM ServiceSAR with xBR Traffic Management The RS8235 Service Segmentation and Reassembly Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA interface with service specific functions in a single package. The ServiceSAR Controller generates and

CN8234

Abstract: BT82
Contextual Info: RS8234 ATM ServiceSAR Plus with xBR Traffic Management The RS8234 Service Segmentation and Reassembly Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA interface with service specific functions in a single package. The ServiceSAR Controller generates and

testbench vhdl ram 16 x 4

Abstract: ram memory testbench vhdl code mem_rd_ sample vhdl code for memory write ram memory testbench vhdl testbench verilog ram 16 x 4 000-3FF PCI32 altera pci pci verilog code
Contextual Info: PCI Testbench User Guide August 2001 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com A-UG-PCITEST-1.0 PCI Testbench User Guide Copyright Copyright  2001 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all

IXP2800

Abstract: ixp2400 rohs Intel IXA SDK Developers Workbench D-128 intel ixa sdk core components ixa sdk IXP2400 IXP2800 microengine
Contextual Info: product brief Intel IXP2800 Network Processor For OC-192/10 Gbps network edge and core applications Product Highlights • Delivers 10 Gbps packet forwarding and traffic management on a single chip ■ Introduces Hyper Task Chaining processing technology that enables deep packet