BGP Search Results

Contextual Info: Agilent N2X IPv4 Routing Emulation Software E7882A Technical Data Sheet Agilent N2X IPv4 Routing Emulation Software integrates the most scalable BGP-4, OSPF, IS-IS and RIP routing protocol emulations available to deliver unparalleled protocol verification and

Contextual Info: Agilent N2X IPv6 Routing Emulation Software E7885A Technical Data Sheet Agilent N2X IPv6 Routing Emulation software integrates the most scalable BGP-4+, OSPFv3, IS-ISv6 and RIPng routing protocol emulations available to deliver unparalleled protocol verification and stress testing on your IPv6

Digital Pulse Counter Two Digit

Contextual Info: MITSUBISHI <DIGITAL ASSP> M35500AFP/BGP FLD VFD CONTROLLER DESCRIPTION/FEATURES • Serial I/O . 4 (CS controller, external clock) • High-breakdown-voltage output port . 26 •

Contextual Info: Or, Call Customer Semes at 1-8Û0-548-S132 USA Only |U^BgpwN | VCA610 <0 < o WIDEBAND VOLTAGE CONTROLLED AMPLIFIER FEATURES APPLICATIONS • • • • • • • • • • • • WIDE GAIN CONTROL RANGE: 80dB SMALL PACKAGE: 8-pin SOIC or DIP WIDE BANDWIDTH: 30MHz

router

Abstract: 5988-9950EN bgp route flap route messages protocol "BGP" "Border Gateway Protocol" "OSPF" "LINK STATE"
Contextual Info: Agilent N2X IPv4 Routing Emulation Software E7882A Technical Data Sheet Agilent N2X IPv4 Routing Emulation Software integrates the most scalable BGP-4, OSPF, IS-IS and RIP routing protocol emulations available to deliver unparalleled protocol verification and

BA9K

Contextual Info: =;/4; @>A>6FGD: >AF:D@:9>6F: CBI:D D:?6K ;QM^_\Q] Jgjc Qm7CI:<<=A: m @E qugrafgle a_n_`gjgrw 1;G5 <G rwnc2 m :7>iY bgcjcarpga qrpclerf 1`cruccl amgj _lb amlr_arq2 m Kmjb nj_rcb amlr_ar _t_gj_`jc m Gmldmpk rm rfc GI jmu tmjr_ec bgpcargtc m Vmaicrq _t_gj_`jc

multibus ARCHITECTURE

Abstract: mcbsp tms 6000
Contextual Info: TMS320VC5416 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS095B – MARCH 1999 – REVISED OCTOBER 1999 D D D D D D D D D D D D D Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU

S-PQFP-G144 footprint

Contextual Info: TMS320VC5410A Fixed-Point Digital Signal Processor Data Manual Literature Number: SPRS139 November 2000 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to

Contextual Info: TMS320VC5416 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS095E – MARCH 1999 – REVISED MAY 2000 D D D D D D D D D D D D D Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU Including a 40-Bit Barrel Shifter and Two

ifr 422 H7

Abstract: ifr 422 h6 49 4h10 remote TMS320C54xTM
Contextual Info: TMS320VC5441 Fixed-Point Digital Signal Processor Data Manual Literature Number: SPRS122A December 1999 – Revised November 2000 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to

transistor marking WC 2C

Abstract: E22/6/AS7620/TMS320C6678/AS7620/NZT6728-datasheet
Contextual Info: TMS320C6678 SPRS691E—November 2010—Revised March 2014 Multicore Fixed and Floating-Point Digital Signal Processor Check for Evaluation Modules EVM : TMS320C6678 1 TMS320C6678 Features and Description 1.1 Features • Eight TMS320C66x DSP Core Subsystems (C66x

TMS320VC541

Contextual Info: SM320VC5416-EP Fixed-Point Digital Signal Processor Data Manual Literature Number: SGUS048 July 2003 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include

tms320vC5402 starter kit

Abstract: BDX 34 TMS320VC5402
Contextual Info: TMS320VC5402 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 D Advanced Multibus Architecture With Three D D D D D D D D D D D D D Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU ,

Contextual Info: TMS320VC5441 Fixed-Point Digital Signal Processor Data Manual Literature Number: SPRS122E December 1999 – Revised April 2002 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

TPSMA*A

Contextual Info: TPSMA6.8 thru TPSMA43A Vishay General Semiconductor Surface Mount PAR Transient Voltage Suppressors High Temperature Stability and High Reliability Conditions FEATURES • Junction passivation optimized design passivated anisotropic rectifier technology

TMS320VC5441

Abstract: TMS320VC5441GGU TMS320VC5441PGF
Contextual Info: TMS320VC5441 Fixed-Point Digital Signal Processor Data Manual Literature Number: SPRS122F December 1999 − Revised October 2008 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

AXP 188

Abstract: btp 128 550 BDP 162 DO-220AA J-STD-002 AXP 209 btp 129 MARKIN CODE 324 arp
Contextual Info: New Product TPSMP6.8 thru TPSMP43A Vishay General Semiconductor High Power Density Surface Mount PAR Transient Voltage Suppressors FEATURES ® • Junction passivation optimized design passivated anisotropic rectifier technology eSMP Series • TJ = 185 °C capability suitable for high reliability

mc 6871 a

Contextual Info: TMS320VC5410A Fixed-Point Digital Signal Processor Data Manual Literature Number: SPRS139F November 2000 – Revised May 2004 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not

app abstract

Contextual Info: TMS320VC5407/TMS320VC5404 Fixed-Point Digital Signal Processors Data Manual Literature Number: SPRS007B November 2001 – Revised July 2003 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

Contextual Info: M65665DSP PICTURE-IN-PICTURE SIGNAL PROCESSING REJ03F0012-0100Z Rev.2.00 Sep.04.2003 Description The M65665DSP is a PIP Picture in Picture signal processing LSI, whose sub-picture input is composite signal or component signals(Y/C or Y/U/V) for NTSC , PAL-M , PAL-N. The built-in field memory (168k-bit RAM) , V-chip

Contextual Info: M65665CFP/SP PICTURE-IN-PICTURE SIGNAL PROCESSING REJ03F0011-0100Z Rev.2.00 Sep.04.2003 Description The M65665CFP/SP is a PIP Picture in Picture signal processing LSI, whose sub-picture input is composite signal or component signals(Y/C or Y/U/V) for NTSC.

Contextual Info: TMS320VC5416 Fixed-Point Digital Signal Processor Data Manual Literature Number: SPRS095O March 1999 – Revised January 2005 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not

10000 series of ECL gates

Contextual Info: 10165F DESCRIPTION LOGIC DIAGRAM The 10165 is a device designed to provide a 3-bit binary coded output for each of 8 in­ put lines. Priority selection circuitry is included so that the output reflects the highest priority input present and ignores lower order inputs. Each of the outputs is

BGY 55

Contextual Info: 1.5SMCJ SERIES SURFACE MOUNT TRANSIENT VOLTAGE SUPPRESSOR VOLTAGE-5 .0 -1 7 0 Volts Peak Pulse Power-1500 Watts _ FEATURES_ • For surface m ounted applications in order to optim ize board space • Low profile package • Built-in strain relief