HMVIP Search Results

CHN 063

Abstract: 16.384Mhz HMVIP TS10 TS11 TS12 TS13 TS14 TS15 XRT86VL38
Contextual Info: TAN-063 April 11, 2005 XRT86VL3x HMVIP High Speed Multiplexed Mode XRT86VL3X Applications Note HMVIP High Speed Backplane Interface Operation and Timing 1 TAN-063 April 11, 2005 XRT86VL3x HMVIP High Speed Multiplexed Mode T1 Transmit HMVIP Backplane Interface

HMVIP

Contextual Info: Backplane Interface TDM/TSI SWITCHES VOICE/DATA 256 x 512 256 x 256 16 10 2 K x 512 512 x 2 K 512 x 512 16L, 32B* 16L, 32B* H.110, H.100, HMVIP 4Kx2K 2Kx4K 1Kx1K 2Kx2K 16L*, 32B* 16L*, 32B* 4Kx2K H.110, H.100, HMVIP 4Kx2K 2Kx4K 2Kx2K 2Kx2K 16L, 32B* 16L, 32B*

MT90812AL1

Abstract: TGE-5 EB32
Contextual Info: MT90812 Integrated Digital Switch IDX Advance Information Mar 2011 Features • • • • • • • • • • • • • • • • • • MT90812AP MT90812AL MT90812APR MT90812AP1 MT90812AL1 MT90812APR1 192 channel x 192 channel non-blocking switching

Contextual Info: Freescale Semiconductor Data Sheet: Document Number: MSC8144E Rev. 10, 8/2008 MSC8144E FC-PBGA–783 29 mm x 29 mm Quad Core Digital Signal Processor • Four StarCore SC3400 DSP subsystems, each with an SC3400 DSP core, 16 Kbyte L1 instruction cache, 32 Kbyte L1 data cache,

Contextual Info: XRT86VX38A 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION JULY 2013 REV. 1.0.0 GENERAL DESCRIPTION The XRT86VX38A is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and Long-haul/Shorthual LIU integrated solution featuring R3 technology

multiplexing e1 frame to e3 frame

Abstract: S1215P S1215 STM MARKING GR-253 TU12 32xDS1
Contextual Info: Product Brief 5 21 S1 UR AM S1215 Amur Deep channelization SONET/SDH to PDH framer and 1K Channels HDLC/ATM/GFP processor Overview SONET/SDH Line Features Tributary Features S1215 (Amur) interfaces with 155Mbps/622Mbps SONET/SDH (1xSTS-12/STM-4, 4xSTS-3/STM-1)

Contextual Info: TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com TMS320C6472 Fixed-Point Digital Signal Processor 1 Features • • • • • • • • • • • Congestion Control • IEEE 1149.6 Compliant I/Os – UTOPIA • UTOPIA Level 2 Slave ATM Controller

TR54016

Abstract: XRT86L38 XRT86VL34 XRT86VL34IB PIN26
Contextual Info: XRT86VL34 QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION JANUARY 2007 REV. V1.2.0 GENERAL DESCRIPTION The XRT86VL34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .

CRC-32

Abstract: FREEDM-32P672 GPIC672 PM7380 RHDL672 PM4314
Contextual Info: PMC-Sierra,Inc. Preliminary PM7380 FREEDM-32P672 Frame Engine and Data Link Manager FEATURES The FREEDM32P672 chip offers the following features: • Single-chip multi-channel HDLC controller with a 66 MHz, 32-bit Peripheral Component Interconnect PCI 2.1 compliant bus for

Diode LT 228d

Abstract: 1E2H SMD making code DV5
Contextual Info: 7: 43 AM PM4323 OCTLIU LT Device ASSP Telecom Standard Product Data Sheet Released ,0 ay co n Th ur sd OCTLIU LT 1M ay ,2 00 8 01 :0 PM4323 of Pa rtm in er In Device Telecom Standard Product Proprietary and Confidential Released Issue No. 5: April 2008 Do

LR 4100 RELAY

Contextual Info: 58 AM TE-32 ASSP Telecom Standard Product Data Sheet Released r, 20 05 12 :5 3: PM4332 y, 13 De ce m be TE-32 in er In co n Tu es da High Density 32 Channel T1/E1/J1 Framer Proprietary and Confidential Released Issue No. 6: November 2005 Do wn lo ad ed by

LR 4100 RELAY

Abstract: PM8316PGI 315-B PM8316-PGI
Contextual Info: PM8316 TEMUX 84 RELEASED DATA SHEET ISSUE 9 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX 10 :3 5: 14 PM PMC-1991437 ,1 3M ar ch ,2 00 6 PM8316 co n Mo nd ay TEMUX 84 DATA SHEET Do wn l oa de d by C on te nt T ea m of Pa rtm in er In HIGH DENSITY T1/E1 FRAMER WITH

ADSP-21535PKB-300

Abstract: EC38J ADSP-21535 Blackfin dsp 131070
Contextual Info: PRELIMINARY TECHNICAL DATA a ADSP-21535 Preliminary Technical Data SUMMARY 300 MHz High-Performance Blackfin DSP Core Two 16-Bit MACs, Two 40-Bit ALUs, Two 40-Bit Accumulators, Four 8-Bit Video ALUs, and a 40-Bit Shifter RISC-Like Register and Instruction Model for Ease of

DMO 565 R

Abstract: dmo 465 Twelve NC Code
Contextual Info: xr XRT86L34 PRELIMINARY QUAD T1/E1/J1 FRAMER/LIU COMBO NOVEMBER 2004 REV. P1.1.6 GENERAL DESCRIPTION The XRT86L34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .

225-ball

Contextual Info: XRT86VL34 PRELIMINARY QUAD T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION JULY 2006 REV. P1.0.8 GENERAL DESCRIPTION The XRT86VL34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless,

0x0360

Abstract: XRT86VL30
Contextual Info: XRT86VL30 PRELIMINARY SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION DECEMBER 2007 REV. P1.0.0 GENERAL DESCRIPTION The XRT86VL30 is a single channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless,

RHDL-12

Abstract: Multilink hdlc DDLL140 PM7389 THDL-12
Contextual Info: PM7389 FREEDM 84A1024 Preliminary Frame Engine and Datalink Manager FEATURES • Single-chip multi-channel packet processor supporting a maximum aggregate bandwidth of 156 Mbit/s for line rate throughput transfers of packet sizes from 40 to 9.6 Kbytes, for up to

sti12

Abstract: ST012 FOS100 MT90820 MT90820AL MT90820AP STO11
Contextual Info: CMOS ST-BUS FAMILY MT90820 Large Digital Switch LDX Advance Information  Features • • • • • • • • • ISSUE 1 2,048 channel non-blocking switch Maintains frame integrity on concatenated channels. Per-channel selection of minimum or constant

vortex modem

Abstract: "Base Transceiver Station" 3g modem circuit 3g router DSLAM JT-G704 PM4354 PM7328 PM7350 PIC-22
Contextual Info: PM4354 COMET-QUAD Four Channel Combined E1/T1/J1 Transceiver/Framer FEATURES • Provides a two-frame payload slip buffer to allow independent backplane and line timing. • Automatically generates and transmits DS-1 performance report messages to ANSI T1.231 and ANSI T1.408

Relays H100

Abstract: H100 IXF3208 LXT3108
Contextual Info: product brief Intel IXF3208 Octal T1/E1/J1 Framer with Intel® On-Chip Performance Report Messaging Product Description The Intel® IXF3208 is an octal framer for T1/E1/J1 and ISDN primary rate interfaces operating at 1.544Mbps or 2.048Mbps. Each framer consists of a receive framer,

thermal overload relay fas

Abstract: CRC-32 PM7383 TD422
Contextual Info: PM7383 FREEDM-32A256 RELEASED DATASHEET PMC-2010336 ISSUE 1 FRAME ENGINE AND DATA LINK MANAGER 32A256 PM7383 FREEDM -32A256 FRAME ENGINE AND DATALINK MANAGER 32A256 DATASHEET PROPRIETARY AND CONFIDENTIAL RELEASED ISSUE 2: AUGUST 2001 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

33091

Abstract: CRC-32 PM7382
Contextual Info: PM7382 FREEDM-32P256 RELEASED DATA SHEET PMC-2010333 ISSUE 3 FRAME ENGINE AND DATA LINK MANAGER 32P256 PM7382 FREEDM -32P256 FRAME ENGINE AND DATALINK MANAGER 32P256 DATA SHEET RELEASED ISSUE 3: AUGUST 2001 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

pc toTv BOX Diagram

Abstract: ZL50117GAG2 ZL50116GAG ZL50117GAG ZL50118GAG ZL50119GAG ZL50120GAG ZL50110 ZL50111 ZL50112
Contextual Info: ZL50115/16/17/18/19/20 32, 64 and 128 Channel CESoP Processors Data Sheet Features March 2009 Ordering Information General • Circuit Emulation Services over Packet CESoP transport for MPLS, IP and Ethernet networks • On chip timing & synchronization recovery across

MEB90812

Abstract: WARBLE TONE GENERATORS intel 8247 circuit diagram of car central lock system conference system MT8952 MT8952B MT90812 MT90812AL MT90812AP
Contextual Info: MT90812 Integrated Digital Switch IDX Advance Information Features • • • • • • • • • • • • • • • • • • 192 channel x 192 channel non-blocking switching 2 local bus streams @ 2Mb/s supports up to 64 channels In TDM mode, the expansion bus supports up