HD100 Search Results

"NOR Gates"

Abstract: HD100101 HD100101F
Contextual Info: H D 100101 T rip le 5 - in p u t O R /N O R G a te s I LOGIC DIAGRAM I PIN ARRANGEMENT »HD100101F • HD100101 Ifc C; B: 21 '¿'S 22 U, As ti 20 nnnnnn Fi 1 \ 19 IK H A , Z Z 2 1' Hj 1 :( m IZ D 4 l r' 5 14 Z n v , U il E i l - 6 7 X 4 111 11 12 D O'

HD100118

Abstract: HD100118F H11H
Contextual Info: H D 100118 5 - w id e O R - A N D /O R - A N D - IN V E R T G a te IL O G IC D IA G R A M I PIN A R R A N G E M E N T ►HD100118F • HD100118 nnnnnn Ci ^ “ Un, J4 C 2S I K ' ; „ C i H; la Ü2 Hi , „ c . K ,£ S •-0 ‘■ « C 6 I" P c * c ; A.C

Contextual Info: H D 100107 Q u in tu p le E x c lu s iv e - O R / N O R G a te s I LO G IC DIAGRAM • PIN A R R A N G E M E N T • HD100107F • HD100107 V.C 1 v.C v-C ^ 24 □ »- 1 n □ *, 3 22 □ 4 21 5 Y .C nnnnnn Ri Rì Aì IX Z D A, 2 r 3 1* Z D * 4 l r> = * Ÿs 1

HD100160

Abstract: HD100160F
Contextual Info: H D 100160 Dual P a rity G e n e ra to rs / C h e c k e r The HD100160 is a Dual Parity for 16 or more bits. The HD100160 also has a Compare C output which allows the circuit to Checker/ Generator. Each half has nine inputs, with the output being high when an even number of inputs

Contextual Info: H D 100117 Triple 2 -w id e O R -A N D /O R -A N D -IN V E R T Gates I PIN ARRANGEMENT •LOGIC DIAGRAM • HD100117 • HD100117F li; IDC CHARACTERISTICS I te m l F.F. Input C u rre n t I ih \: A V ee = - 4 . 2 to - 4 . 8 V , Vcc = V cca = GND, T a = 0 t o + 8 5 ° C

Contextual Info: H D 100181 4 - b i t B in a r y / B C D A L U The HD100181 perform s eight logic operations and eight a rith m e tic operations on a pair o f 4 -b it words. The operating mode is determ ined by signals applied to the Select Sn inputs, as shown in the F unction Select table. In add itio n to

EZ 720

Abstract: ez 920
Contextual Info: H D 1 0 0 1 4 5 — 1 6 X 4 R e a d / W rite R e g is te r F ile The HD100145 is a 64-bit Register File organ­ ized as 16 words of four bits each. Separate can be forced LO W by a H IG H signal on either of address inputs for Read A R n and Write (A W n)

hd100102f

Contextual Info: H D 100102 Quintuple 2-input O R /N O R G ates • P IN A R R A N G E M E N T I L O G IC D IA G R A M • HD100102 , c V 'C v.C • HD100102F 3 w : ¿in i r: •l Ai C I'ec = □ a. c r ; h. 2« Jv, .v,C h I 1* .,- c : lh * r UUUUULI !<i v .C V. in Y. 11

HD100151F

Contextual Info: H D 1001S1 Hex D -typ e F lip -F lo p s HD100151 contains six master/slave flip -flo p s w ith CPa and CPb are lo w and transfers to the slave True and C om plem ent outputs. A pair o f Common Clock inputs CPa and CPb and com m on Master when CPa o r CPb (or bo th) go high. The MR

Contextual Info: H D 10 0 1 6 4 16-input Multiplexer Their decoding is shown in the truth table. Output data polarity is the same as the selected input data. The HD100164 is a 16-input Multiplexer. Data paths are controlled by four select line Sq —S3 . • PIN ARRANGEMENT

Contextual Info: HD100166 9-bit Comparator The HD100166 is a 9-bit Magnitude Comparator The which compares the arithm etic value o f two 9-bit which provides the wire O R functions by trying outputs do not have pull down resistors, words and indicates whether one word is greater

Contextual Info: H D 100163 Dual 8 -in p u t M u ltip le xers The HD100163 is a dual 8-input Multiplexer. The Data Select Sn inputs determine which bit (An and Bn) will be presented at the Outputs (Z a and Zg respectively). The same bit (0—7) will be selected for both the Z^ and Zg output.

Contextual Info: H D 100155 Quad. M u l t i p l e x e r s / L a t c h e s The HD100155 contains four transparent latches, high signal from either D 0 or D ! to an output. The each of which can accept and store data from two Select inputs can be tied together fo r applications

Contextual Info: HD100163 Dual 8 - i n p u t M u ltiplexers The H D 1 0 0 1 6 3 is a dual 8-inp ut M ultip lexer. The Data Select Sn inputs determ ine which bit (A n and Bn) will be presented at the O utputs (Z a and Zg respectively). The same bit (0 —7) w ill be selected fo r both the Z ^ and Zg output.

Contextual Info: H D 100102 Q u in tu p le 2 -input O R / N O R G a te s I LO G IC D IAGRAM • PIN A RR A N G EM EN T • HD100102 • HD100102F K ,C □ " C 4 V C > r.C V tr.Z v .C b, i\ > i 2" * W : \t H ' - X 17 y 1». □ v Ill 1- > : 11 14 i.' n ID C C H A R A C T E R IS T IC S

Contextual Info: HD100160 Dual Parity G enerators/C hecker The HD100160 is a Dual Parity for 16 or more bits. The HD100160 also has a Compare C output which allows the circuit to Checker/ Generator. Each half has nine inputs, with the output being high when an even number of inputs

Contextual Info: H D 100131 Triple D -typ e F lip -F lo p s The HD100131 contains three D-type Master Slave Direct Clear CDn inputs. Data enters a master Flip Flops with true and complement outputs, a Common Clock (CPc), and Master Set (MS) and when both CPn and CPc are low and transfers to a

HD100136

Abstract: HD100136F
Contextual Info: H D 100136 4-stage Counter/S hift R eg is ter the Q j output. The dual nature of this TC /Q 3 output and the D o /C ET input means that one interconnection from one stage to the next higher The HD100136 operates as either a modulo-16 up/down counter or as a 4-bit bidirectional shift

HD100163

Abstract: HD100163F
Contextual Info: H D 100163 Dual 8-inp ut M ultiplexers The HD100163 is a dual 8-input Multiplexer. The Data Select Sn inputs determine which bit (An and Bn) will be presented at the Outputs (Z a and Zg respectively). The same bit (0—7) will be selected for both the Z^ and Zg output.

hd100102F

Abstract: HD100102
Contextual Info: H D 100102Quintuple 2-input O R /N O R Gates I LOGIC DIAGRAM I PIN ARRANGEMENT * HD100102F • HD100102 r B, A, C lij B* * 24 23 22 V V > nnñfíno. lo II I Yi Yi tim ira T r Y, V< V'c \\ca •Top Vie | DC C H A R A C T E R IS T IC S ( - 4 .2 Vee — 4.8V, V cc =

HD100K

Contextual Info: GENERAL INFORMATION OF HD100K SERIES •FEATURES cation of inverters, and it avoids the problems of number of external parts, power dissipation, pro­ • Stability Built-in temperature and voltage compensation cir­ cuits assure the stable output characteristics within

AABJ

Contextual Info: HD100166 9-bit Comparator The HD100166 is a 9-bit Magnitude Comparator The outputs do not have pull down resistors, which provides the wire O R functions by trying which compares the arithmetic value of two 9-bit words and indicates whether one word is greater

Contextual Info: H D 100171 T rip le 4 - in p u t M u ltip le x e rs w ith E n ab le The HD100171 contains Triple 4-input multi- complement outputs. A high on the Enable input plexers which share a common decoder {inputs SO E forces all true outputs low (see truth table),

HD100181

Abstract: bcd alu HD100181F
Contextual Info: H D 100181 4 - b it B i n a r y / B C D A LU The HD100181 performs eight logic operations and eight arithm etic operations on a pair of 4-bit words. The operating mode is determined by The circuit uses internal lookahead carry to minimize delay to the F outputs and to the ripple