HAD26 Search Results

Cx2829

Abstract: ,national semiconductor Linear brief lb-3
Contextual Info: CX28250 ATM Physical Interface PHY Devices The CX28250 is an ATM-SONET Physical Layer (PHY) device with an integrated, PLL clock and data recovery (CDR) circuit. This device has optimized SONET framer functions for mapping ATM cells to SONET payloads for edge switch applications, and

DSP56300

Abstract: DSP56301 SC20
Contextual Info: 4 CORE CONFIGURATION 4.1 INTRODUCTION This chapter contains DSP56300 Core configuration details specific to the DSP56301 device. For more information on the described registers or modules, refer to the appropriate chapters in the DSP56300 Core spec. 4.2 CHIP OPERATING MODES

IM336

Abstract: DSP56000 DSP56300 DSP56301 XC56301PW80 HA10-HA3 IM324 IM308 jtag pinout Nippon capacitors
Contextual Info: MOTOROLA Order this document by: DSP56301/D SEMICONDUCTOR TECHNICAL DATA DSP56301 Advance Information 24-BIT DIGITAL SIGNAL PROCESSOR The DSP56301 is a member of the DSP56300 core family of programmable CMOS Digital Signal Processors DSPs . This family uses a high performance, single-clock-cycle-per-instruction

cpcap motorola 3.2 51

Abstract: f3a14
Contextual Info: MOTOROLA Order Number: DSP56301/D Rev. 4, 10/2001 Semiconductor Products Sector Technical Data DSP56301 24-Bit General-Purpose Digital Signal Processor The DSP56301 is a member of the DSP56300 core family of programmable CMOS Digital Signal Processors DSPs . This family uses a high-performance, single clock cycle per instruction engine providing a twofold

SA1381

Abstract: SS823 RDATA13 3RA61 AC21T n25h VSS1490 bwd9 HAD44 HAD48
Contextual Info: A B C D REVISIONS ZONE LTR CN8237/CX29704 PCB:BT01-D255-011 A DESCRIPTION INITIAL APPROVED DATE RELEASE 1 1 DL1 DELAYLINE 2.5NS 1 2 U7 3 CN8237 SEGMENTATION SCLK0 R124 18 DL2 B3SCLK0 A3SCLK1 R116 18 DELAYLINE 2.5NS POWER VDD PINS E7, E8, E11, E12, E15, E16

BT8233EHFB

Abstract: 5969b l8233
Contextual Info: R O C K W E L L Network access S E M I C O N D U C T O R Bt8233 ATM ServiceSAR with S Y S T E M S xBR Traffic Management datasheet PROVIDING HIGH SPEED MULTIMEDIA CONNECTIONS September 1998 Bt8233 ATM ServiceSAR with xBR Traffic Management The Bt8233 Service Segmentation and Reassembly Controller integrates in a single

"complementary code"

Abstract: "M-ary orthogonal keying" "Complementary Code Keying"
Contextual Info: ISL3874A TM Data Sheet P RE L I M I N A RY May 2001 Wireless LAN Integrated Medium Access Controller with Baseband Processor with Mini-PCI The Intersil ISL3874A Wireless LAN Integrated Medium Access Controller with Integrated Baseband Processor is part of the PRISM 2.4GHz radio

I960CA

Abstract: CRC10 RS8234 RS8250 on-demand multicast messages
Contextual Info: RS8234 ATM ServiceSAR Plus with xBR Traffic Management The RS8234 Service Segmentation and Reassembly Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA interface with service specific functions in a single package. The ServiceSAR Controller generates and

I960CA

Abstract: CN8236 CX28250EVM Bt8223
Contextual Info: CN8236 ATM ServiceSAR Plus with xBR Traffic Management The CN8236 Service Segmentation and Reassembly Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA level 1 or 2 interface with service-specific functions in a single package for AAL0, 3/4, and 5 operations.

1301 dc he nv

Abstract: PB16-PB19 sedt SC02TH HP-47 PF30U
Contextual Info: MOTOROLA Order this document by: DSP56305/D SEMICONDUCTOR TECHNICAL DATA DSP56305 Advance Information SINGLE CHIP CHANNEL CODEC DIGITAL SIGNAL PROCESSOR Motorola designed the DSP56305 to deliver the high performance required to support Global System for Mobile GSM communications applications that use digital signal processing to

K30A transistor

Abstract: POWER COMMAND HM 1211 manual K30A POWER COMMAND HM 1211 power generation POWER COMMAND HM 1211 DSP56301V HM 1211 transistor k30a B-28 DSP56300
Contextual Info: DSP56301 USER’S MANUAL DSP56301UM Rev. 4, November 2005 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations not listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224

Contextual Info: RS8235 Endstation ATM ServiceSAR with xBR Traffic Management The RS8235 Service Segmentation and Reassembly Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA interface with service specific functions in a single package. The ServiceSAR Controller generates and

MPU-401

Abstract: PC97 PT-101 "multiplexed command" schmitt trigger IC echo reverb chorus ic ess modem audiodrive
Contextual Info: PRELIMINARY AGOGO-XP AudioDrive Solution Product Brief DESCRIPTION Legacy DOS Game Support The AGOGO-XP PCI Audio Accelerator represents a new generation of architecture that not only meets the new demands of advanced PC audio applications but also enables the integration of a complete

HP16

Abstract: DSP56000 DSP56300 DSP56301 A2061
Contextual Info: Freescale Semiconductor Technical Data DSP56301 24-Bit Digital Signal Processor 52 6 6 3 Memory Expansion Area Triple Timer Host Interface ESSI SCI X Data Program RAM RAM 4096 x 24 bits 2048 × 24 bits Default (Default) Y Data RAM 2048 × 24 bits (Default)

CN8237EBGB

Abstract: CX29704 RS8234 RS8235 PCI x1 express PCB dimensions artwork BC 5473
Contextual Info: CN8237 ATM OC-12 ServiceSAR Plus with xBR Traffic Management The CN8237 Service Segmentation and Reassembly ServiceSAR Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA 1 or 2 interface with service-specific functions in a single package for AAL0 and AAL5 operations. The ServiceSAR

Contextual Info: RS8235 Endstation ATM ServiceSAR with xBR Traffic Management The RS8235 Service Segmentation and Reassembly Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA interface with service specific functions in a single package. The ServiceSAR Controller generates and

CN8234

Abstract: BT82
Contextual Info: RS8234 ATM ServiceSAR Plus with xBR Traffic Management The RS8234 Service Segmentation and Reassembly Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA interface with service specific functions in a single package. The ServiceSAR Controller generates and

Cx2829

Abstract: TXC24 0x46-RXLIN "network interface cards" Trec Part Numbering System GR
Contextual Info: CX28250 ATM Physical Interface PHY Devices The CX28250 is an ATM-SONET Physical Layer (PHY) device with an integrated, PLL clock and data recovery (CDR) circuit. This device has optimized SONET framer functions for mapping ATM cells to SONET payloads for edge switch applications, and

B56A

Abstract: Cx2829 J311 B21AD
Contextual Info: CX28250 ATM Physical Interface PHY Devices The CX28250 is an ATM-SONET Physical Layer (PHY) device with an integrated, PLL clock and data recovery (CDR) circuit. This device has optimized SONET framer functions for mapping ATM cells to SONET payloads for edge switch applications, and

MCM54800AJ70

Abstract: 4814P-002-472 QS3244SO motorola u1620 HC94U-27 TSM10701SDV CR12061001JVCA AT29LV512 DSP56301 MCM6706AJ12
Contextual Info: CHAPTER 13 DSP56301 APPLICATION DEVELOPMENT MODULE HARDWARE DESCRIPTION 13.1 BOARD ARCHITECTURE The DSP56301 ADM has various options to facilitate evaluation of the different features of the chip.These options are outlined in this chapter with a statement on the default factory jumpers the ADM is shipped with.

DSP56000

Abstract: DSP56300 DSP56301 PC1197
Contextual Info: Freescale Semiconductor Technical Data DSP56301 Rev. 10, 7/2006 DSP56301 24-Bit Digital Signal Processor 52 6 6 3 Memory Expansion Area Triple Timer Host Interface ESSI SCI X Data Program RAM RAM 4096 x 24 bits 2048 × 24 bits Default (Default) Y Data RAM

First line 7aa ed tms 3874 9v voltage regulator

Abstract: RS8250EBGC tms 3874 9v voltage regulator code 9y mrd 14b R7173-11 18AF d725 11AF PE-68508
Contextual Info: R O C K W E L L Network access S E M I C O N D U C T O R S Y S T E M S RS8250/1/2/3/4/5 ATM Physical Interface Devices - ATM PHY datasheet PROVIDING HIGH SPEED MULTIMEDIA CONNECTIONS September 1998 Preliminary Information This document contains information on a product under development. The parametric information contains target

BSDE

Abstract: compaq 486 motherboard diagram rockwell E3 plus RS8234 RS8235 RS8235EPF RS8251 IR remote control transmitter circuit
Contextual Info: R O C K W E L L Network access S E M I C O N D U C T O R S Y S T E M S RS8235 Endstation ATM ServiceSAR with xBR Traffic Management datasheet PROVIDING HIGH SPEED MULTIMEDIA CONNECTIONS September 1998 Preliminary Information This document contains information on a product under development. The parametric information contains target

K30A transistor

Abstract: K30A 1 HP25 731 motorola transistor k30a Nippon capacitors
Contextual Info: DSP56301 User’s Manual 24-Bit Digital Signal Processor DSP56301UM/AD Revision 2.0, August 1999 OnCE and Mfax are trademarks of Motorola, Inc. Intel“ is a registered trademark of the Intel Corporation. All other trademarks are those of their respective owners.