H15 227 1 Search Results

transistor Kd 505

Abstract: k534 TRANSISTOR D410 transistor DA 218 b058 8060 transistor 805S-IG32 1G22 1G5.1 8060-1G6
Contextual Info: TH IS DRAW ING IS A C O N TR O LLE D DO C U M EN T. REVISIONS T ^ st DATE - p 0 0 28N0V2006 ECO — 05 — Ö9 78 8058 & 8060 Series DWN APVD Kb i/ n d e s c r ip t io n L J Transisto r Sockets 8060-1G11 8060-1G6 FEATURES: — 1^ PERFORMANCE SPECIFICATIONS:

m 208 b1

Abstract: EPM7256E EPM7256S
Contextual Info: EPM7256E & EPM7256S Dedicated Pin-Outs ver. 1.0 Dedicated Pin 160-Pin PQFP 1 , (2) 192-Pin PGA (2) 208-Pin RQFP/PQFP (3) INPUT/GCLK1 INPUT/GCLRn INPUT/OE1 INPUT/OE2/GCLK2 TDI (4) TMS (4) TCK (4) TDO (4) GND 139 141 140 142 146 23 98 135 3, 18, 32, 47, 57, 64, 66, 81,

84 pin PGA socket

Contextual Info: From: DocuFACTSUn] Ph* 949-253-7438 16038801932 Pomona 8-20-99 ll:59ara p. 4 of 6 Model 5998A 240 Lead QFP Test Clip with PGA, .50 mm Lead Pitch These new test clips provide the user with an easy means to connect instrumentation to the SMT leads of 240 pin plastic, metal and ceramic quad

erni 533202

Abstract: KSG-173 erni 533410 594073 533410 IEC60603-2 KSG-203 ERNI 594079 DIN 41612 connector male H11 ERNI 334415
Contextual Info: Connectors DIN 41612/IEC 60603-2 and completions ERNI-electronic components quality assessed according to CECC 75101-801 106 Catalog E 074484 04/04 Edition 6 www.erni.com Table Of Contents Catalog E 074484 04/04 Edition 6 www.erni.com 107 DIN 41612 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

EPM2210

Abstract: h9 317 P7U10 EPM1270 EPM240 EPM570 F256 F324 EPM2210 324
Contextual Info: Dedicated Pin Information for the MAX II EPM2210 / EPM2210G Devices Version 1.2 Dedicated Pin IO/GCLK0 IO/GCLK1 IO/GCLK2 IO/GCLK3 IO/DEV_OE IO/DEV_CLRn TDI TMS TCK TDO GNDINT GNDIO VCCINT 1 VCCIO1 (2) VCCIO2 (2) VCCIO3 (2) VCCIO4 (2) No Connect (N.C.)

Contextual Info: TOP VIEW Not to Scale 8 +VS FB 2 7 OUT –IN 3 6 NC +IN 4 5 –VS 07040-001 PD 1 NC = NO CONNECT Figure 1. 8-Lead LFCSP (CP) ADA4857-1 FB 1 8 PD –IN 2 7 +VS +IN 3 6 OUT –VS 4 5 NC NC = NO CONNECT 07040-002 TOP VIEW (Not to Scale) Figure 2. 8-Lead SOIC (R)

T25 4 h5

Abstract: AE23 AF23 EP20K60E 356-pin 215 bga BGA128
Contextual Info: EP20K60E I/O Pins ver. 1.1 I/O & VREF Bank 8 8 8 8 – 8 8 8 8 8 – 8 – Pad Number Orientation Pin/Pad Function 144-Pin TQFP 1 208-Pin PQFP (1) 240-Pin PQFP (1) 144-Pin 324-Pin 356-Pin FineLine BGA FineLine BGA BGA 1 2 3 4 5 6 7 8 9 10 11 12 13 – –

AE23

Abstract: EP20K100E AF-1
Contextual Info: EP20K100E I/O Pins ver. 1.0 I/O & VREF Bank 8 8 8 – 8 – 8 8 8 8 8 – 8 8 8 8 8 – 8 8 8 8 8 – 8 8 8 8 8 – – – – 8 8 8 Pad Number Orientation Pin/Pad Function 144-Pin 208-Pin 240-Pin 144-Pin 324-Pin 356-Pin TQFP 1 PQFP (1) PQFP (1) FineLine BGA FineLine BGA BGA

EP20K100E

Abstract: t25 4 j5
Contextual Info: Pin Information for the APEX EP20K100E Device Version 1.5 I/O & VREF Bank Pad Number Orientation Pin/Pad Function 144-Pin TQFP 1 208-Pin PQFP (1) 240-Pin PQFP (1) 144-Pin 324-Pin FineLine BGA FineLine BGA 356-Pin BGA 8 8 8 — 8 — 8 8 8 8 8 — 8 8

AE23

Abstract: EP20K100E
Contextual Info: EP20K100E I/O Pins ver. 1.1 I/O & Pad Pin/Pad VREF Number Function Bank Orientation 144-Pin 208-Pin 240-Pin 144-Pin TQFP PQFP PQFP FineLine 1 (1) (1) BGA 324-Pin FineLine BGA 356-Pin BGA 8 8 8 – 8 – 8 8 8 8 8 – 8 8 8 8 8 – 8 8 8 8 8 – 8 8 8 8 8

FF 400 R14

Abstract: 208pin PQFP BB 298 431 A1 aa g15 BB 313 BB 438 BB 444 EPM3512A aa t 224
Contextual Info: EPM3512A Dedicated Pin-Outs ver. 1.0 Dedicated Pin INPUT/GCLK1 INPUT/GCLRn INPUT/OE1 INPUT/OE2/GCLK2 TDI 1 TMS (1) TCK (1) TDO (1) GNDINT GNDIO 208-Pin PQFP 184 182 183 181 176 127 30 189 75, 82, 180, 185 6, 14, 32, 40, 50, 51, 72, 84, 94, 108, 116, 134, 152, 158, 174,

D4136

Abstract: m 208 b1 PQFP ALTERA 160 EPM7256A EPM7256AE EPM7256E EPM7256S EPM7512AE m64196 L6M15
Contextual Info: EPM7256A and EPM7256AE Dedicated Pin-Outs ver. 1.0 Dedicated Pin 100-Pin TQFP 100-Pin FineLine BGA INPUT/GCLK1 87 A6 INPUT/GCLRn 89 B5 INPUT/OE1 88 B6 INPUT/OE2/GCLK2 90 A5 TDI 1 4 A1 TMS (1) 15 F3 TCK (1) 62 F8 TDO (1) 73 A10 GNDINT 38, 86 D6, G5 144-Pin TQFP 208-Pin PQFP 256-Pin FineLine BGA

la 4507

Abstract: P06P03 43BJ ST1302 g3328 Am29434
Contextual Info: ADVANCED MICRO 0257525 DEVICES M d F | D5S7SHS ADVANCED MI CRO D E V I C E S 8 9 D OOEM^S 7 D p .lfS ’01 24935 Am29423 a 10K-ECL 32-Bit Parallel Multiplier ADVANCE INFORMATION DISTINCTIVE CHARACTERISTICS 32-Blt Three-Bus Architecture Registers can be made transparent

AX125

Abstract: FBGA 896 896-Pin
Contextual Info: Axcelerator Family FPGAs Package Pin Assignments 180-Pin CSP A1 Ball Pad Corner 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P Figure 3-1 • 180-Pin CSP Bottom View Note For Package Manufacturing and Environmental information, visit Resource center at

EP3C25 pin diagram

Abstract: EP3C25 pin guideline
Contextual Info: Pin Information for the Cyclone III EP3C25 Device Version 1.5 Notes 2 , (3) Bank Number VREFB Group Pin Name / Function B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VCCD_PLL3 GNDA3

RTAX2000S

Abstract: RTAX1000S-SL cga 624 RTAX1000S RTAX250S RTAX2000 624 CCGA SL D8 E26 RTAX4000S CCGA
Contextual Info: RTAX-S/SL RadTolerant FPGAs Package Pin Assignments 208 207 206 205 160 159 158 157 208-Pin CQFP Pin 1 1 2 3 4 156 155 154 153 Ceramic Tie Bar 208-Pin CQFP 108 107 106 105 101 102 103 104 53 54 55 56 49 50 51 52 Figure 3-1 • 208-Pin CQFP Top View Note

Contextual Info: Pin Information for the Cyclone III EP3C16 Device Version 1.4 Notes 1 , (2) PT-EP3C16-1.4 Copyright 2013 Altera Corp. Bank Number VREFB Group Pin Name/ Function B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0

EPM1270T144

Abstract: ALTERA EPM1270F256 epm1270f256 256 pin diagram EPM1270 F256 Y1057 TQFP 256
Contextual Info: Dedicated Pin Information for the MAX II EPM1270 / EPM1270G Devices Version 1.4 144-Pin TQFP 18 20 89 91 60 61 34 33 35 36 17, 54, 92, 128 10, 26, 47, 65, 83, 99, 115, 135 VCCINT 1 VCCIO1 (2) VCCIO2 (2) VCCIO3 (2) VCCIO4 (2) No Connect (N.C.) Total User I/O Pins

EPM1270

Abstract: F256 TQFP 256 h15 227 1 EPM1270G C9A10 EPM1270T144
Contextual Info: Dedicated Pin Information for the MAX II EPM1270 / EPM1270G Devices Version 1.5 Dedicated Pin IO/GCLK0 IO/GCLK1 IO/GCLK2 IO/GCLK3 IO/DEV_OE IO/DEV_CLRn TDI TMS TCK TDO GNDINT GNDIO 144-Pin TQFP 18 20 89 91 60 61 34 33 35 36 17, 54, 92, 128 10, 26, 47, 65, 83, 99, 115, 135

729-Pin

Abstract: Axcelerator FPGAs AX125 IO126PB3F11 AG18 FBGA 896 896-Pin Axcelerator Family FPGAs
Contextual Info: Axcelerator Family FPGAs Package Pin Assignments 180-Pin CSP A1 Ball Pad Corner 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P Figure 3-1 • 180-Pin CSP Bottom View Note For Package Manufacturing and Environmental information, visit Resource center at

Contextual Info: COM’L MIL a PAL16R8 Family Advanced Micro Devices 20-pin TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS • As fast as 7.5 ns maximum propagation delay ■ Easy design with PALASM software ■ Popular 20-pln architectures: 16L8,16R8, 16R6,16R4

EP1C12

Abstract: F256 F324
Contextual Info: Pin Information for the Cyclone EP1C12 Device Final version 1.2 Bank Number B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREF Bank VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1

XC5402

Abstract: XC5406 XC5410
Contextual Info: f l XILINX XC5400 Hardwire Array Family Preliminary Product Specification Features Description • Mask Programmed version of the XC5200 Field Programmable Gate Array FPGA - Specifically designed for easy XC5200 conversion - Significant cost reduction for high volume

5200 FPGA

Abstract: PC8421
Contextual Info: SIXILINX* XC5400 Hardwire Array Family Preliminary Product Specification Features Description • Mask Programmed version of the XC 5200 Reid Programmable G ate Array FPGA - Specifically designed for easy XC 5200 conversion - Significant cost reduction for high volume