GATE LEVEL SIMULATION Search Results

verilog code for implementation of prom

Abstract: Reconfiguration BINARY SWITCH verilog code for switch
Contextual Info: New UNISIM Libraries for Functional VHDL W ith the new UNISIM libraries from Xilinx, you can simulate RTL behavioral code with gate-level instantiations, gate-level descriptions imported from schematics, and gate-level VHDL and Verilog descriptions exported from synthesis,

max 1786

Abstract: SRAM timing ATL60
Contextual Info: SRAMs-3.3-6/96 Memory ATL60 SRAMs Compiled Gate Level Compiled Gate Level SRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Common Single Port SRAM Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

ATL60

Abstract: 4 inputs OR gate
Contextual Info: ATL60SRAMs-3.4-04/98 Memory ATL60 SRAMs Compiled Gate Level Compiled Gate Level SRAMs . 9-2 Common Single Port SRAM Sizes: Table. 9-2

ATL35

Contextual Info: ATL35 Memory SRAMs-1.0-12/97 Memory ATL35 0.35µ Compiled Gate Level SRAMs Compiled Gate Level SRAMs . 9-2 Common Single Port SRAM Sizes: Table. 9-2

ATL35

Abstract: sram spice ATMEL 744
Contextual Info: ATL35 Memory SRAMs-1.0-12/97 Memory ATL35 0.35µ Compiled Gate Level SRAMs Compiled Gate Level SRAMs . 9-2 Common Single Port SRAM Sizes: Table. 9-2

static SRAM single port

Abstract: al5b ATMEL 910 din 74 ATL35 PRAM12X32R1W1
Contextual Info: ATL35 Memory SRAMs-1.2-04/99 Memory ATL35 0.35µ Compiled Gate Level SRAMs Compiled Gate Level SRAM Loading . 9-2 Common Single Port SRAM Sizes: Table. 9-2

bsu 479

Abstract: atmel 912 asynchronous RAM atmel 0848 "32K x 32" SRAM 32K 4K x 8 Synchronous Dynamic RAM atmel 0529
Contextual Info: ATL25 Memory SRAMs - 1.1 - 08/00 Memory ATL25 0.25µ Compiled Gate Level SRAMs Compiled Gate Level SRAM Loading . 9-2 Common Single Port SRAM Sizes: Table. 9-2

vhdl code for sdram controller

Abstract: UART using VHDL verilog code for uart communication elf32-nios verilog code for stream processor vhdl code for character display uart verilog code uart c code nios processor dump memory avalon verilog
Contextual Info: Simulating Nios Embedded Processor Designs February 2003, ver. 2.1 Introduction Application Note 189 Simulation is an important part of the design process. Register transfer level RTL simulation verifies that a design performs as the designer intended, while gate-level simulation considers device-level timing to

Contextual Info: Simulating Nios Embedded Processor Designs April 2002, ver. 1.1 Introduction Application Note 189 Simulation is an important part of the design process. Register transfer level RTL simulation verifies that a design performs as the designer intended, while gate-level simulation considers device-level timing to

GAL programmer schematic

Abstract: vhdl code ispLSI 1K LATTICE plsi 3000 PDS-211 daisy chain verilog
Contextual Info: pDS+ Exemplar Software TM RTL behavior. The high-level design paradigm supported by Exemplar Logic encompasses three distinct design steps: device-independent specification and simulation; constraint-independent, architecture-specific implementation; and gate-level verification.

ATMEL 634

Abstract: ambit rev 4 LSI CMOS GATE ARRAY PO11V5 MH1099 MH1242 705uA
Contextual Info: Features • • • • • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal System Level Integration Technology Cores on Request SRAM and TPRAM; Gate Level or Embedded

ATMEL 634

Abstract: MH1099 MH1242 PO11V5 dual lvds vhdl
Contextual Info: Features • • • • • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal System Level Integration Technology Cores on Request SRAM and TRAM (Gate Level or Embedded)

Contextual Info: Features • • • • • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal System Level Integration Technology Cores on Request SRAM and TRAM (Gate Level or Embedded)

MH1099

Abstract: MH1242 PO11V5 4138G
Contextual Info: Features • • • • • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal System Level Integration Technology Cores on Request SRAM and TRAM (Gate Level or Embedded)

AT 2005A

Abstract: L33 TRANSISTOR ATMEl 837 ARM CORE 1825 verilog code for UART with BIST capability 8 bit risc microprocessor using vhdl L33v verilog code for 32 bit risc processor 2005A-ASIC-06 MIPS64 5kf
Contextual Info: Features • • • • • Available in Gate Array, Embedded Array or Standard Cell High-speed, 75 ps Gate Delay, 2-input NAND, FO = 2 nominal Up to 13.7 Million Used Gates and 1516 Pins 0.18µ Geometry in up to Six-level Metal System-level Integration Technology

PO88

Abstract: ttl buffer AOI222 AOI2223 AOI2223H AOI222H MH1099 MH1242 PRD21 PRD29V5
Contextual Info: Features • High Speed - 170 ps Gate Delay - 2 input NAND, FO=2 nominal • Up to 1.6 Million Used Gates and 596 pads, with 3.3V, 3V, and 2.5V libraries • System Level Integration Technology Cores on request: SRAM and TRAM (Gate Level or Embedded) • I/O Interfaces:

ATMEL 634

Abstract: ambit rev 4 C 828 dual mcga SRAM edac A101 A201 MH1099E MH1156E MH1242E
Contextual Info: Features • • • • • • • • • Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries High Speed - 180 ps Gate Delay - 2 Input NAND, FO = 2 nominal System Level Integration Technology Cores on Request Memories: SRAM and TPRAM, Gate Level or Embedded, with EDAC

Contextual Info: HUF76121SK8 Data Sheet April 1999 8A, 30V, 0.023 Ohm, N-Channel, Logic Level UltraFET Power MOSFET • Logic Level Gate Drive • 8A, 30V • Simulation Models - Temperature Compensated PSPICE and SABER Electrical Models - SPICE and SABER Thermal Impedance Models

Contextual Info: HUF76105SK8 Data Sheet May 1999 5.5A, 30V, 0.050 Ohm, N-Channel, Logic Level UltraFET Power MOSFET • Logic Level Gate Drive • 5.5A, 30V • Ultra Low On-Resistance, rDS ON = 0.050Ω • Simulation Models - Temperature Compensated PSPICE and SABER

AN7254

Abstract: AN9321 AN9322 HUF76132SK8 HUF76132SK8T MS-012AA TB334
Contextual Info: HUF76132SK8 Data Sheet September 1999 11.5A, 30V, 0.0115 Ohm, N-Channel, Logic Level UltraFET Power MOSFET • Logic Level Gate Drive • 11.5A, 30V • Simulation Models - Temperature Compensated PSPICE and SABER Electrical Models - Spice and SABER Thermal Impedance Models

A101

Abstract: A201 MH1099E MH1156E MH1242E MH1332E AMI 1108
Contextual Info: Features • • • • • • • • • • • Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries High Speed - 180 ps Gate Delay - 2 Input NAND, FO = 2 nominal System Level Integration Technology Cores on Request Memories: SRAM and TPRAM, Gate Level or Embedded, with EDAC

A101

Abstract: A201 MH1099E MH1156E MH1242E MH1332E atmel 838 atmel edac dsp radiation hard
Contextual Info: Features • • • • • • • • • • • Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 nominal System Level Integration Technology Cores on Request Memories: SRAM and TPRAM, Gate Level or Embedded, with EDAC

A101

Abstract: A201 MH1099E MH1156E MH1242E MH1332E HEX TO DECIMAL ATMEL 220 dsp radiation hard
Contextual Info: Features • • • • • • • • • • • • Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 nominal System Level Integration Technology Cores on Request Memories: SRAM and TPRAM, Gate Level or Embedded, with EDAC

H92B

Abstract: db1n DUAL-PORT STATIC RAM AT24K
Contextual Info: SRAMs Compiled gate level SRAMs Atmel offers a variety of SRAMs compiled within the ATL80 series of gate arrays. These SRAMs utilize the standard metallization process, and are implemented using the gate array sites to form memory elements. The SRAMs are fully static with