FPB32 Search Results

T801

Abstract: speedo meter N10E inmos transputer T800 TIN30 T800 transputer T801-20 2AF3 w188
Contextual Info: 127 IMS T801 transputer □ Preliminary Data FEATURES 32 bit architecture 33 ns internal cycle time 30 MIPS peak instruction rate 4.3 Mflops (peak) instruction rate Debugging support 64 bit on-chip floating point unit which conforms to IEEE 754 4 Kbytes on-chip static RAM

74F74

Abstract: inmos transputer T225 transputer Inmos t805 FP 8022 74F04 800E 801C T222 T225
Contextual Info: IMS T225 16-bit transputer FEATURES H 16 bit architecture H 33 ns internal cycle time H 30 MIPS peak instruction rate H Debugging support H 4 Kbytes on-chip static RAM H 60 Mbytes/sec sustained data rate to internal memory H 64 Kbytes directly addressable external memory

ic t805

Abstract: IMS T805-F20E inmos transputer inmos transputer T225 T425 T800 t225 Inmos t805 IMS T805-G20E MEMAD11
Contextual Info: SGS-THOMSON IMS T805E •HI 32-bit floating-point transputer - Extended temperature EATURES 32 bit architecture 50 ns internal cycle time 20 MIPS peak instruction rate 2.8 Mflops (peak) instruction rate Pin compatible with IMS T800 Floating Point Unit Debugging support

FPB33

Abstract: FPB35
Contextual Info: 224-225.qxp 7/22/2010 3:02 PM Page 224 Pushbutton Series Fiberglass Enclosures Pushbutton Series The Cooper Crouse-Hinds Pushbutton Series offer a solution for applications requiring an enclosure with multiple pre-drilled openings for pushbuttons available in 30mm and 22mm configurations. The

T225E

Abstract: imst225
Contextual Info: _ 16-bit transputer FEATURES • 16 bit architecture ■ 33 ns internal cycle time ■ 30 MIPS peak instruction rate ■ Debugging support ■ 4 Kbytes on-chip static RAM ■ 60 Mbytes/sec sustained data rate to internal memory ■

imst400

Abstract: 25f0 T222 transputer FP 1117 aj T400 clock FP 801 transputer T222 T225 inmos transputer T225
Contextual Info: SGS-THOMSON IMS T225 L K g lT IM M ! 16 -bit transputer EATURES 16 bit architecture 33 ns internal cycle tim e 30 M IPS pea k instruction rate D ebugging support 4 Kbytes on-chip static RAM 60 M bytes/sec sustained data rate to internal m em ory 64 Kbytes directly addressable external m em ory

FP 1117 aj

Abstract: a9yv T222 transputer 2BF4 T222 inmos transputer T225 200ppm 2p23 IMST400
Contextual Info: SGS-THOMSON IMS T225E 16-bit transputer - Extended temperature FEATURES • 16 bit architecture ■ 50 ns internal cycle tim e ■ 20 M IPS peak instruction rate ■ D ebugging support ■ 4 Kbytes on-chip sta tic RAM ■ 40 M bytes/sec sustained data rate to internal m em ory

IMST414

Abstract: IMS T400 ST T4 1060 0922 imst400 IMST225 inmos T414 T805-20 R3174 si9590 inmos transputer
Contextual Info: SGS-THOMSON IM S T 4 0 0 Low cost 32-bit transputer FEATURES • 32 bit architecture ■ 50 ns internal cycle time ■ 20 MHz only ■ 20 MIPS peak instruction rate ■ 10 MIPS sustained instruction rate ■ Pin compatible with IMS T805, IMS T800, IMS T425

FPB32

Abstract: k 319 FPB33 FMP0606C FMP12 FMP1210
Contextual Info: Fiberglass Enclosures Pushbutton Series 5E The Cooper Crouse-Hinds Pushbutton Series offer a solution for applications requiring an enclosure with multiple pre-drilled openings for pushbuttons available in 30mm and 22mm configurations. The notched keyhole design and the ability to order up to 25 holes,

T425

Abstract: T400 T414 T800 T805 inmos transputer T425 T800 transputer IMST425
Contextual Info: IMS T425 32-bit transputer FEATURES 32 bit architecture 40 ns internal cycle time 25 MIPS peak instruction rate Pin compatible with IMS T805, IMS T800, IMS T400 and IMS T414 Debugging support 4 Kbytes on-chip static RAM System Services 100 Mbytes/sec sustained data rate to internal

T400 600

Abstract: IMS T414
Contextual Info: Low cost 32-bit transputer FEATURES • 32 bit architecture ■ 50 ns internal cycle time ■ 20 MHz only ■ 20 MIPS peak instruction rate ■ 10 MIPS sustained instruction rate ■ Pin compatible with IMS T805, IMS T800, IMS T425 and IMS T414 ■ 2 Kbytes on-chip static RAM

T225E

Abstract: ST225
Contextual Info: w # S G S -m O M S O N IMS T225E 16-bit transputer - Extended temperature FEATURES • 16 bit architecture ■ 50 ns internal cycle time ■ 20 MIPS peak instruction rate ■ Debugging support ■ 4 Kbytes on-chip static RAM ■ 40 Mbytes/sec sustained data rate to internal memory

Contextual Info: S G S -T H O M S O N S IMS T225E s L lP T M lM i 16-bit transputer - Extended temperature FEATURES H 16 bit architecture H 50 ns internal cycle time H 20 MIPS peak instruction rate H Debugging support H 4 Kbytes on-chip static RAM H 40 Mbytes/sec sustained data rate to internal

74F04

Abstract: 74F74 800E 801C T222 T225 T225E Inmos T222
Contextual Info: IMS T225 16-bit transputer FEATURES 16 bit architecture 33 ns internal cycle time 30 MIPS peak instruction rate Debugging support 4 Kbytes on-chip static RAM 60 Mbytes/sec sustained data rate to internal memory 64 Kbytes directly addressable external memory

T222 transputer

Abstract: 74F74 800E 801C T222 T225 IMST222 T225E
Contextual Info: IMS T225E 16-bit transputer – Extended temperature FEATURES 16 bit architecture 50 ns internal cycle time 20 MIPS peak instruction rate Debugging support 4 Kbytes on-chip static RAM 40 Mbytes/sec sustained data rate to internal memory 64 Kbytes directly addressable external memory

AD T805

Abstract: B50R MEMAD11 T805 IMS T805-F25S IMST805 transputer Inmos t805 inmos transputer T225 inmos transputer T425
Contextual Info: 32-bit floating-point transputer FEATURES • 32 bit architecture ■ 40 ns internal cycle time ■ 25 MIPS peak instruction rate ■ 3.6 Mflops (peak) instruction rate ■ ■ Pin compatible with IMS T800, IMS T425, IMS T400 and IMS T414 Debugging support

Inmos t805

Abstract: IMS T805-F20E T425 T800 IMST800 21-F5 REAL32
Contextual Info: IMS T805E 32-bit floating-point transputer – Extended temperature FEATURES APPLICATIONS Scientific and mathematical applications High speed multi processor systems High performance graphics processing – HUD/HDD displays Supercomputers Workstations and workstation clusters

t425

Abstract: SGS thomson power schottky 8000000C sgs thomson 23-F1 KJH T6 IMST425 inmos transputer T425
Contextual Info: w # S G S -T H O M S O N IM < 5 , kT # D ïiin g M iiiL iK g T Â E g n e i ,M & _ T 4 2 5 32-bit transputer FEATURES 32 bit architecture 40 ns internal cycle time 25 MIPS peak instruction rate Pin compatible with IMS T805, IMS T800, IMST400 and IMS T414

sbl 20100

Abstract: T425-X25S MEMAD11 inmos transputer T425
Contextual Info: ^•7 # DMD g(fii ilL[l(gTO©[i!!in(gI / = T S G S -T H O M S O N IM S T 4 2 5 32-bit transputer FEATURES ■ 32 bit architecture ■ 40 ns internal cycle time ■ 25 MIPS peak instruction rate ■ Pin compatible with IMS T805, IMS T800, IMS T400 and IMS T414

CQ 2AF1

Abstract: IMST425 IMS T400 Inmos T222
Contextual Info: 32-bit transputer FEATURES • 32 bit architecture ■ 40 ns internal cycle time ■ 25 MIPS peak instruction rate ■ Pin compatible with IMS T805, IMS T800, IMS T400 and IMS T414 ■ Debugging support ■ 4 Kbytes on-chip static RAM ■ 100 Mbytes/sec sustained data rate to internal

Contextual Info: SGS-THOMSON IMS T225 • H I 16-bit transputer EATURES 16 bit architecture 33 ns internal cycle time 30 MIPS peak instruction rate Debugging support 4 Kbytes on-chip static RAM 60 Mbytes/sec sustained data rate to internal memory 64 Kbytes directly addressable external memory

inmos T414

Abstract: inmos T400 12u-1919-g19 25f5 T400 600 inmos transputer T425 T400 clock T800 transputer AD T805 IMS T414
Contextual Info: IMS T400 Low cost 32-bit transputer FEATURES H 32 bit architecture H 50 ns internal cycle time H 20 MHz only H 20 MIPS peak instruction rate H 10 MIPS sustained instruction rate H Pin compatible with IMS T805, IMS T800, IMS T425 and IMS T414 H 2 Kbytes on-chip static RAM

Contextual Info: S G S -1 H 0 M S 0 N « t i m i I g ï M a M Ê IMS T400 i Low cost 32-bit transputer FEATURES 32 bit architecture 50 ns internal cycle time 20 MHz only 20 MIPS peak instruction rate 10 MIPS sustained instruction rate Pin compatible with IMS T805, IMS T800, IMS T425

IMSC100

Abstract: IMS T800 CPU STI 7110 transputer LONGSUM LED T9000 u44X IMST9000 Edd 44 inmos transputer
Contextual Info: 55 IMS T9000 transputer I . tre y mos Preliminary Information FEATURES Instruction set com patible with the IMS T805 Pipelined superscalar m icro-architecture W orkspace cache Programmable m em ory interface 4 Gbyte physical address space 16 Kbyte instruction and data cache