FP7N10LE Search Results

Contextual Info: • 430Z271 0054745 0T2 fKj HARRIS V D SEMICONDUCTOR February1994 ■ HAS RFD7N10LE, RFD7N10LESM FP7N10LE 7A, 100V, ESD Rated, Avalanche Rated, Logic Level N-Channel Enhancement-Mode Power MOSFETs MegaFETs Features Packaging • 7A, 100V JEDEC TO-220AB

FF175

Abstract: 268E-5
Contextual Info: RFD7N10LE, RFD7N10LESM, FP7N10LE H A R R IS S E M I C O N D U C T O R 7A, 100V, 0.300 Ohm, N-Channel, Logic Level, Power MOSFETs January 1998 Features Description • 7A, 100V These are N-Channel power MOSFETs manufactured using the MegaFET process. This process, which uses feature

7n10le

Abstract: AN7254 AN7260 RFD7N10LE RFD7N10LESM RFP7N10LE pspice model for ttl TC247
Contextual Info: S E M I C O N D U C T O R February 1994 RFD7N10LE, RFD7N10LESM FP7N10LE 7A, 100V, ESD Rated, Avalanche Rated, Logic Level N-Channel Enhancement-Mode Power MOSFETs MegaFETs Features Packaging • 7A, 100V JEDEC TO-220AB TOP VIEW • rDS(ON) = 0.300Ω • 2KV ESD Protected

Contextual Info: P *3 3 S RFD7N10LE, RFD7N10LESM, FP7N10LE 7A, 100V, 0.300 Ohm, N-Channel, Logic Level, Power MOSFETs January 1998 Features Description • 7A, 100 V These are N-Channel power MOSFETs manufactured using the MegaFET process. This process, which uses feature

FP7N10LE

Abstract: JEDEC TO-251AA RFD7N10LE RFP4N05L RFP4N06L RFD7N10LESM 7n10l
Contextual Info: RFP4N05L RFP4N06L Harris A u g u s t 19 91 N-Channel Logic Level Power Field-Effect Transistors L2FET Package Features T0-220A B TOP VIEW • 4A, 5 0 V and 60 V • rD S {0 N ) = ° - 8 n DRAIN (FLANGE) • Design O ptim ized for 5 V G a te Drives • Can b e D riven D irectly from Q M O S, NM O S, T T L Circuits

7N10LE

Abstract: FP7N10LE RFD7N10LESM9A TO-220 package thermal resistance pspice model for ttl RFD7N10LE RFD7N10LESM RFP7N10LE TB334 TC1-1-13
Contextual Info: RFD7N10LE, RFD7N10LESM, FP7N10LE S E M I C O N D U C T O R 7A, 100V, 0.300 Ohm, N-Channel, Logic Level, Power MOSFETs January 1998 Features Description • 7A, 100V These are N-Channel power MOSFETs manufactured using the MegaFET process. This process, which uses feature

pspice model for ttl

Abstract: 7n10l FP7N10LE 268E-5 TC1-1-13 358e9 pspice model for CMOS TRS-10
Contextual Info: m HARRIS RFD7N10LE, RFD7N10LESM FP7N10LE U U S E M I C O N D U C T O R February 1994 7 A, 100V, ESD Rated, Avalanche Rated, Logic Level N-Channel Enhancement-Mode Power MOSFETs MegaFETs Packaging Features JEDEC TO-220AB TOP VIEW • 7A, 100V • r DS(ON) = 0 .3 0 0 Q