FLAG Search Results

74ALS616

Abstract: 74als61
Contextual Info: S N 54A LS616, SN 54A LS617. S N 74A LS616, SN 74A LS617 16-BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS D2840, APRIL 1984-REVISED SEPTEMBER 1985 • D etects and Corrects Single-Bit Errors • D etects and Flags Dual-Bit Errors S N S 4 A L S 6 1 6 . S N 5 4 A IS 6 1 7 . . J D PACKAGE

Contextual Info: SN74ACT7881 1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS227C - FEBRUARY 1993 - REVISED FEBRUARY 1996 • Member of the Texas Instruments Wldebus Family • Independent Asynchronous Inputs and Outputs • Input-Ready, Output-Ready, and Half-Full Flags

Contextual Info: 54AC11853, 74AC 11853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS TI0157— D3473, MARCH 1990 54AC11B53 . . . JT PACKAGE 74AC11853 . . . DW OR NT PACKAGE High-Speed Bus Transceivers with Parity Generator/Checker TOP VIEW Parity Error Flag Open-Drain Output • Register for Storage of the Parity Error Flag

d8253

Contextual Info: SN74AS632A 32 BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUIT D 3 3 9 7 , JAN U AR Y 1990 • Detects and Corrects Single-Bit Errors • Detects and Flags Dual-Bit Errors • Built-In Diagnostic Capability • Fast W rite and Read Cycle Processing Times

Contextual Info: SN 54ALS616, S N 5 4 A L S 6 1 7 , S N 74 A LS 6 16 . S N 7 4 A L S 6 1 7 16-BIT P A R A LLE L ERROR DETECTION AN D CORRECTION CIRCUITS D 2 8 4 0 , A P R IL 1 9 8 4 - R E V IS E D M A Y 1 9 8 6 • Detects and Corrects Single-Bit Errors • Detects and Flags Dual-Bit Errors

Contextual Info: SN54ACT3641 1024 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGBS309A - AUGUST 1995 - REVISED APRIL 1998 • Free-Running CLKA and CLKB Can Be Asynchronous or Coincident • Output-Ready and Almost-Empty Flags Synchronized by CLKB • Clocked FIFO Buffering Data From Port A

marking aa5

Abstract: NCV360SNAET1G NCV360SNAFT1G marking code vey 10000 mf capacitor uDFN-6 On semiconductor date Code tsop-5 UDFN6
Contextual Info: NCP360, NCV360 USB Positive Overvoltage Protection Controller with Internal PMOS FET and Status FLAG The NCP360 disconnects systems at its output when wrong VBUS operating conditions are detected at its input. The system is positive overvoltage protected up to +20 V.

094.71

Abstract: finder 94.8 9474 finder finder 94.03 finder 86.10.0.024.0000 94.54.1 c34r Diode a2
Contextual Info: 55 Series - Miniature General Purpose Relays 7 -10 A 55.12 55.13 55.14 - P.C.B. versions - AC or DC coils - Lockable test button and mechanical flag indicator as standard on 2 and 4 CO relays types - Sockets and accessories: see 94, 99 and 86 series - RT III wash tight version available

Contextual Info: MTE Advance Information D • SöböMSb D GG2G5 3 3f l b ■ lllir n lll MNHS January 1991 NATRA M H S M 67202 HI-REL DATA SHEET 1kX 9 CMOS PARALLEL FIFO FEATURES EMPTY, FULL AND HALF FLAGS IN SINGLE DEVICE MODE RETRANSMIT CAPABILITY BI-DIRECTIONAL APPLICATIONS

CY7C4255

Abstract: CY7C4265 CY7C42X5
Contextual Info: CY7C4255 CY7C4265 8K/16K x 18 Deep Sync FIFOs Features are 18 bits wide and are pin/functionally compatible to the CY7C42X5 Synchronous FIFO family. The CY7C4255/65 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide

C4558

Abstract: C4554 C4557 c455 CY7C455-14JI CY7C455 CY7C456 CY7C457 CY7C447
Contextual Info: CY7C455 CY7C456 CY7C457 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags • Depth Expansion Capability • 52-pin PLCC and 52-pin PQFP Features • High-speed, low-power, first-in first-out FIFO memories • 512 x 18 (CY7C455)

Contextual Info: electronic June 1992 M 67203 HI-REL DATA SHEET 2k X 9 CMOS PARALLEL FIFO FEATURES . FIRST-IN FIRST-OUT DUAL PORT MEMORY . FAST ACCESS TIME : 35 TO 55 ns . . EMPTY, FULL AND HALF FLAGS IN SINGLE DEVICE MODE WIDE TEMPERATURE RANGE : - 55°C TO + 125°C . RETRANSMIT CAPABILITY

Contextual Info: T&B Catalog Number: UPC Number: Description: RBD14-188A Status: Active 78621076990 Fully Insulated Nylon Female - 187 Series Flag Disconnects For Wire Range 16-14 Length 0.74, Tab Size .187 x .020 , Blue WEB_USE -US Cutsheet PDF Catalog Link

67201A

Contextual Info: T em ic M67201A/M67202A S e m i c o n d u c t o r s 512 x 9 & 1 K x 9 CMOS Parallel FIFO Introduction T he M 67201A /202A im plem ent a first-in first-out algorithm , featuring asynchronous read/w rite operations. T he FU LL and E M PTY flags prevent data overflow and

honeywell hx3000

Abstract: HX3000 RHDSP24 DSP24 mxt2416 dsp24s 405F RHtMMU24 MMU24 e01a05
Contextual Info: DSP Architectures RHtMMU24 Transform Your World TM Rad Hard triple Memory Management Unit Data Sheet X3 RESET SYSCLK EN SYSTEM CONTROL TC TCP PO ACTIVE FLAGS SYSCLK START MEMW MEMOE CCOMI CS DIR HOST INTERFACE MEMORY CONTROL CCOMR R/W RHtMMU24 CSWAP A0 A1

A4490

Abstract: CDH74 NR6045 NRG4026
Contextual Info: A4490 Triple Output Step-Down Switching Regulator Features and Benefits Description ▪ Three buck converters ▪ 4.5 to 34 V input voltage range ▪ 550 kHz fixed frequency ▪ Multiphase switching ▪ Independent control of each converter ▪ Power-on-reset flag

4AC17

Abstract: texas instruments fifo cascaded SN74ACT7808
Contextual Info: SN74ACT7808 2048 x 9 STROBED FIRST-IN, FIRST-OUT MEMORY _SCAS205B - FEBRUARY 1991 - REVISED SEPTEMBER 1995 Load Clocks and Unload Clocks Can Be Asynchronous or Coincident * 2048 Words by 9 Bits • Expansion Logic for Depth Cascading 9 Empty, Full, and Half-Full Flags

CI 7473

Abstract: A10C SN74ABT7819
Contextual Info: SN74ABT7819 512 x 18 x 2 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCBS125B —JULY 1992 - REVISED AUGUST 1934 Microprocessor Interface Control Logic Programmable Almost-Full/Almost-Empty Flags Fast Access Times of 9 ns With a 50-pF Load and Simultaneous Switching Data

Contextual Info: 552 54F/74F552 Connection Diagrams Octal Registered Transceiver W ith Parity and Flags b4 b5 Description T T □ : ~28~1 b 3 Œ 27] Be □ l T h e 'F 5 5 2 o c ta l tra n s c e iv e r c o n ta in s tw o 8 -b it re g is te rs fo r te m p o ra ry b7 [ T s to ra g e o f d a ta flo w in g in e ith e r d ire c tio n . E ach re g is te r h a s its o w n c lo c k

sfe 5,5 ma

Abstract: CD3024 PD3024
Contextual Info: >rJ , J Am 29C?33/834 CMOS Parity Bus Transceivers PRELIMINARY > > 3 3 DISTINCTIVE CHARACTERISTICS • • • Low-power CMOS - ICC Static = 80 //A High-speed bidirectional bus transceiver for processor organized devices Error flag with open-collector output

DIODE B34

Abstract: Diode 133 B34 b34 diode ON B34 DIODE on B34
Contextual Info: 0 .OPTEK Product Bulletin OPB 68 O July 1996 Slotted Optical Flag Switch Type OPB68O Features • • • • Phototransistor output Mechanical switch replacem ent Printed circuit board mounting Enhanced signal to noise ratio Description The O PB68O consists of an NPN

SN74ACT7811

Abstract: SN74ACT7881 SN74ACT7882 SN74ACT7884
Contextual Info: SN74ACT7881 1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS227A- FEBRUARY 1993 - REVISED JUNE 1994 Member of the Texas Instruments Wldebus Family * Input-Ready, Output-Ready, and Half-Full Flags Independent Asynchronous Inputs and Outputs Read and Write Operations Can Be

LA 7804 ON

Abstract: ci LA 7804 ON SN74ACT7804 SN74ALVC7804 W256
Contextual Info: SN74ALVC7804 512x18 FIRST-IN, FIRST-OUT MEMORY SCAS432 - JANUARY 1995 DL PACKAGE TOP VIEW • Operates at 3-V to 3.6-V V c c * Load Clock and Unload Clock Can Be Asynchronous or Coincident RESET [ 1 • Low-Power Advanced CMOS Technology D17 [ 2 * Full, Empty, and Half-Full Flags

CD3024

Abstract: PD3024 AM2S
Contextual Info: Am 29833A/834A - Am 29853A/854A Parity Bus Transceivers PRELIMINARY DISTINCTIVE CHARACTERISTICS High-speed bidirectional bus transceiver for processor organized devices Error flag with open-collector output Generates odd parity for all-zero protection Buffered direction three-state control