FIFO Search Results

Contextual Info: TL16C550C ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL SLLS177B- MARCH 1994 - REVISED MARCH 1996 • Programmable Auto-RTS and Auto-CTS • In Auto-CTS Mode, CTS Controls Transmitter • In Auto-RTS Mode, RCV FIFO Contents and Threshold Control RTS

TMS4C2970

Abstract: 4C2973-24 TMS4C2971 Bit Field Memory
Contextual Info: TMS4C2973 245760 BY 12-BIT FIELD MEMORY SMGS672 - OCTOBER 1997 • 2949120 Bits of Memory • Organization: 245760 Words x 12 Bits • Single 3.3-V Power Supply ± 10% Tolerance • Upwardly and Pin-to-Pin Compatible With TMS4C2970 and TMS4C2971 • 2-Port Memory With FIFO Operation

Contextual Info: New Product Highlights TL16C750 Extended FIFO Asynchronous Communications Element I Description The TL16C750 performs parallel-to-serial and serial-to parallel conversion on data characters transmitted to and from the CPU. The ’750 features a 64-byte FIFO, in

Contextual Info: TL16C550B ASYNCHRONOUS COMMUNICATIONS ELEMENT SLLS136A - JANUARY 1994 - REVISED MARCH 1996 • Capable of Running With All Existing TL16C450 Software • After Reset, All Registers Are Identical to the TL16C450 Register Set • In the FIFO Mode, Transmitter and Receiver

Contextual Info: TEXAS INSTR A S I C / M E M O R Y b4E D • 8^1725 ODflEbCH 3 3b M J I SN74ABT7816 64 X 36 X 2 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCBS129-JULY1992 Free-Running CLKA and CLKB May Be Asynchronous or Coincident Two Independent 64 x 36 Clocked FIFOs Buffering Data in Opposite Directions

TSB12LV41

Contextual Info: DATA TRANSMISSION C o n s u m e r Electronics G o Digital w ith N e w Link-Layer Controllers he TSB12LV41 for MPEG2/DSS receiving IEEE 1394 packets simulta­ and the TSB12LV42 for digital neously. A separate, implemented video data streams are TTs latest 8-Kbyte FIFO, accessible via the BDIF,

Contextual Info: SN54ACT3641 1024 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGBS309A - AUGUST 1995 - REVISED APRIL 1998 • Free-Running CLKA and CLKB Can Be Asynchronous or Coincident • Output-Ready and Almost-Empty Flags Synchronized by CLKB • Clocked FIFO Buffering Data From Port A

Contextual Info: TL16C552 DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO _ SLLS102B - DECEMBER 1990 - REVISED MARCH 1996 • IBM PC/AT Compatible • Programmable Serial Interface Characteristics for Each Channel: - 5-, 6-, 7-, or 8-bit Characters

Contextual Info: SN54ACT3641 1024 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGBS309A – AUGUST 1995 – REVISED APRIL 1998 D D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A to Port B Memory Size: 1024 × 36

Contextual Info: 8- AND 9-BIT ASYNCHRONOUS FIFOS Benefits Features 8- and 9-Bit Asynchronous FIFOs 5-2 • Multiple-speed sort options • Design flexibility • Depth from 256 to 4K words • Optimize depth for specific application • Fast data-access time of 15 ns • Increased system performance

1030J6C

Abstract: C1030B TDC1030B6C 1030J6A
Contextual Info: m m m T D C 1 0 3 0 M First-In First-Out Memory 64 Words by 9 Bits Cascadable T he T R W T D C 1 0 3 0 is an expandable, First-In First-Out FIFO m em ory organized as 64 w o rd s by 9 bits. A 1 5 M H z data rate m akes it ideal in high-speed ap p li­ cations. Bu rst data rates of 18MFHz can be obtained in

diagrams of 16450 UART

Abstract: RRD-B30M75 SNLS378B
Contextual Info: PC16550D PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs† Literature Number: SNLS378B PC16550D Universal Asynchronous Receiver Transmitter with FIFOs General Description Features The PC16550D is an improved version of the original 16450 Universal Asynchronous Receiver Transmitter UART

AN2232-02

Abstract: AN2232L-02 CSTLSM00G53 ADM213 FT2232D AN2232L-01 MAXIM 9737 93LC ft2232dr SP213
Contextual Info: Document No.: FT_000173 FT2232D DUAL USB TO SERIAL UART/FIFO IC Datasheet Version 2.05 Clearance No.: FTDI# 127 Future Technology Devices International Ltd FT2232D Dual USB to Serial UART/FIFO IC The FT2232D is a dual USB to serial UART or FIFO interface with the following advanced

RS-485-2W

Abstract: RS485-4W RS-4852 16C550C MOXA rs232 9 pin female serial port connector max 422 3.3 V DB44-MALE 114EL CP-114EL/EL-I
Contextual Info: Serial Expansion and Extension Solutions CP-114EL/EL-I 4-port RS-232/422/485 PCI Express boards with optional 2 KV isolation CP-114EL ››PCI Express x1 compliant ››921.6 Kbps maximum baudrate for super fast data transmission ››128-byte FIFO and on-chip H/W, S/W flow control

CD40105BMS

Abstract: IOH15
Contextual Info: CD40105BMS CMOS FIFO Register December 1992 Features Description • 4 Bits x 16 Words CD40105BMS is a low-power first-in-first-out FIFO “elastic” storage register that can store 16 4-bit words. It is capable of handling input and output data at different shifting rates. This

d8227

Abstract: 16384
Contextual Info: PRELIMINARY SPACE ELECTRONICS INC. HIGH-SPEED EPI-CMOS 16384 X 9-BIT PARALLEL FIFO SPACE PRODUCTS 7206ERP W 1 28 VCC D8 2 27 D4 D3 3 26 D5 D2 4 25 D6 D1 5 24 D7 D0 6 23 FL/RT XI 7 22 RS FF 8 21 EF Q0 9 20 XO/HF Q1 10 19 Q7 Q2 11 18 Q6 Q3 12 17 Q5 Q8 13 16

16C450

Abstract: MS-018 PC16552 PC16C552 PLCC44 SC16C2552B SC16C2552BIA44 ST16C2552
Contextual Info: SC16C2552B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s max. , with 16-byte FIFOs Rev. 03 — 12 February 2009 Product data sheet 1. General description The SC16C2552B is a two channel Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel

SC16IS752 application

Abstract: HVQFN-32 SC16IS752 SC16IS762 SC16IS752IBS 16C450 HVQFN32 SC16IS752IPW SC16IS762IPW TSSOP28
Contextual Info: SC16IS752/SC16IS762 Dual UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support Rev. 07 — 19 May 2008 Product data sheet 1. General description The SC16IS752/SC16IS762 is an I2C-bus/SPI bus interface to a dual-channel high

SM5838AS

Contextual Info: SM5838AS 5120 x 8-bit Synchronous FIFO OVERVIEW The SM5838AS is a 5120 × 8-bit synchronous FIFO first in, first out high-speed line buffer. Internally, it employs static CMOS circuits which mean that it effectively has limitless data hold times. It can operate at

SC28l921

Abstract: 16-BYTE HVQFN48 PLCC44 QFP44 SC26C92 SC28L92 SC28L92A1A SC28L92A1B SCC2692
Contextual Info: SC28L92 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter DUART Rev. 07 — 19 December 2007 Product data sheet 1. General description The SC28L92 is a pin and function replacement for the SCC2692 and SC26C92 operating at 3.3 V or 5 V supply with added features and deeper FIFOs. Its configuration on

SMD T6s

Abstract: 16C450 16C550 HVQFN24 MO-220 SC16C750B SC16C751BIBS
Contextual Info: SC16C751B 5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs Rev. 02 — 10 October 2008 Product data sheet 1. General description The SC16C751B is a Universal Asynchronous Receiver and Transmitter UART used for serial data communications. Its principal function is to convert parallel data into serial

C401 diode

Abstract: 10DC IR transistor 10dc ir C4016 C4019 C401 CY7C401 CY7C402 CY7C403 C4013
Contextual Info: CY7C401/CY7C403 CY7C402/CY7C404 64 x 4 Cascadable FIFO 64 x 5 Cascadable FIFO Features words. Both the CY7C403 and CY7C404 have an output enable OE function. • 64 x 4 (CY7C401 and CY7C403) 64 x 5 (CY7C402 and CY7C404) High-speed first-in first-out memory (FIFO)

CY7C4255V

Abstract: CY7C4265V CY7C4275V CY7C4285V CY7C42X5V
Contextual Info: fax id: 5422 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V PRELIMINARY 8K/16K/32K/64Kx18 Low Voltage Deep Sync FIFOs Features Functional Description The CY7C4255/65/75/85V are high-speed, low-power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to

infrared transmitter receiver rs232

Abstract: SC28l921 QFP44 footprint 16-BYTE PLCC44 QFP44 SC26C92 SC28L92 SC28L92A1A SC28L92A1B
Contextual Info: SC28L92 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter DUART Rev. 06 — 26 April 2006 Product data sheet 1. General description The SC28L92 is a pin and function replacement for the SCC2692 and SC26C92 operating at 3.3 V or 5 V supply with added features and deeper FIFOs. Its configuration on