FFS 642 Search Results

virtex-6 ML605 user guide

Abstract: UG353 vhdl code 8 bit LFSR ML605 UCF FILE virtex 5 fpga utilization simple 32 bit LFSR using verilog 65Gbps SP006 virtex-5 ML605 user guide aurora GTX
Contextual Info: LogiCORE IP Aurora 8B/10B v5.3 DS637 January 18, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP Aurora 8B/10B core implements the Aurora 8B/10B protocol using the high-speed serial transceivers on the Virtex -5 LXT, SXT, FXT, and TXT

virtex-6 ML605 user guide

Abstract: virtex-7 sp605 verilog code 8 bit LFSR UG476 ARM v7 block diagram virtex7
Contextual Info: LogiCORE IP Aurora 8B/10B v7.1 DS797 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP Aurora 8B/10B core supports the AMBA protocol AXI4-Stream user interface. The core implements the Aurora 8B/10B protocol using the

virtex-7

Abstract: Aurora LX240T virtex7 vhdl coding for error correction and detection xilinx virtex-7 Spartan-6 LXT LX240T-FF1156 kintex 7
Contextual Info: LogiCORE IP Aurora 8B/10B v8.1 DS797 April 24, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP Aurora 8B/10B core supports the AMBA protocol AXI4-Stream user interface. The core implements the Aurora 8B/10B protocol using the

ML421

Abstract: 2310 fx ML320 ML423 ML325 sp002 DS083 DS112 ML321 ML323
Contextual Info: Aurora v3.0 DS128 September 19, 2008 Product Specification Introduction LogiCORE IP Facts The LogiCORE IP Aurora core implements the Aurora protocol on Virtex -II Pro and Virtex-4 FX FPGAs. The core can use up to 20 Virtex-II Pro or 24 Virtex-4 FPGA RocketIO™ multi-gigabit transceivers

PC1238

Abstract: 1238H UPC1238H PPC12 PC1238V QQEZ773 nec 14 tv diagram jiPC1238 MPC123
Contextual Info: N E C 6427525 N ELECTRONICS ELECTRONICS INC OSE D | t,M27525 0G22772 7 ^| ~ 05E INC 22772 BIPOLAR ANALOG INTEGRATED C IR C U IT M P C 12 3 8 P C 1238H T - 7 V - O5 -0 I 10 W A F P O W E R AMPL IF IE R T h e ^ P C 1 2 3 8 is an a ud io pow er a m p lifie r designed fo r m edian H i- F i stereo set and T V set sound pow er a m p lifie r.

nec 7915

Abstract: LF356 equivalent L9810 7915 pin configuration PC356 LF356 RS 7915 7915 nec
Contextual Info: N E C ELECTRONI CS 6427525 N E C I NC öl E LECTRONICS I>e | b427SSS O O lC m ^ 81C 10093 INC NEC Electronics Inc. _ ' The //PC356 is a J-FET input operational am plifier with matched P-channel ion implanted J-FETs. In addition to

M6420

Abstract: AM6112 dip mica capacitor dip guard capacitor
Contextual Info: Am6420 H igh S p e e d 1 2 -B it A c c u ra te S a m p le -a n d -N o ld PRELIMINARY DATA DISTINCTIVE CHARACTERISTICS FUNCTIONAL DESCRIPTION • • • • • • • • • • • The Am 6420 is a m onolithic sam ple-and-hold circuit con­ sisting of a gated high perform ance operational amplifier

IC Speakerphone

Contextual Info: EX4R X R -T 6 4 2 1 Speakerphone Control IC FU N CTIO N AL BLO CK DIAGRAM G E N ER A L DESCRIPTIO N The XR-T6421 is a monolithic integrated circuit for use in high performance speakerphone systems. It is designed to p ro v id e a ll c o n tro l fu n c tio n s for th e X R - T 6 4 2 0 - 2

Contextual Info: Am148 •Am149 Quad 741 Operational Amplifiers Distinctive Characteristics • • • • 741 op am p o p e ra tin g c h a ra cte ristics L o w s u p p ly c u rre n t d ra in — 0 .6 m A /a m p lifie r Class A B o u tp u t state — no crossover d is to rtio n

UPC1342V

Abstract: UPC1342 transistor C 2987A transistor 2sc 4267 C1342V 40WTHD 2SD2013 PC1342V 2SC2987 C2987
Contextual Info: N E C 6427525 N E C ELECTRONICS INC DSE D | t,427S25 GG230t,4 7 | ~ E LE CTRON IC S INC 05E 23064 D BIPOLAR ANALOG INTEGRATED CIRCUIT MP C I 3 4 2 V 7~z-7 t/t2S'-C>/ 5 0 to 1 1 0 W POWER A M P LIFIE R DRIVER DESCRIPTION ¿¿PC1342V is a integrated monolithic circuit designed for 50 W to 110 W class HiFi audio power amplifier and consists of

10091

Abstract: UPC318 upc318c LM318 10092 nec T-79-07-10
Contextual Info: N E C EL E C T R O N IC S 6427525 N E C INC ö l DE J b 4 2 7 S E S ODlOOñ'í 8IC 10089 ELECTRONICS INC NEC NEC Electronics Inc. D ^ T-79-07-10 \ yUPC318 HIG H -SPEED O PERA TIO N A L A M P L IF IE R D escription The¿/PC31 8 is a precision high-speed operational am pli­

Contextual Info: AC Output Buffered Modules • Compatible w ith 5 & 15 Volt Logic Systems • Buffered Inverting and Non-Inverting Modules • Zero Voltage AC Switching cava d m Buffered output modules contain addi­ tional internal amplification to reduce drive requirements to a level suitable for

Contextual Info: H D66108- RAM-Provided 165-Channel LCD Driver for Liquid Crystal Dot Matrix Graphics Description The HD66108T under control of an 8-bit MPU can drive a dot matrix graphic LCD (liquid-crystal display) employing bit-mapped display with support

Contextual Info: AC Output Buffered Modules • Compatible w ith 5 & 15 Volt Logic Systems • Buffered Inverting and Non-Inverting Modules • Zero Voltage AC Switching cava d m Buffered output modules contain addi­ tional internal amplification to reduce drive requirements to a level suitable for

Contextual Info: AC Output Buffered Modules • Compatible w ith 5 & 15 Volt Logic Systems • Buffered Inverting and Non-Inverting Modules • Zero Voltage AC Switching cava d m Buffered output modules contain addi­ tional internal amplification to reduce drive requirements to a level suitable for

MDIO clause 45 specification

Abstract: MDIO clause 45 MDIO vhdl code for ethernet csma cd vhdl code for ethernet mac spartan 3 vhdl code for mac interface Xilinx ISE Design Suite 9.2i ffs 642 verilog code for frame synchronization SPARTAN-6 mgt
Contextual Info: XAUI v9.1 DS266 December 2, 2009 Product Specification Introduction LogiCORE IP Facts The LogiCORE IP XAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between data-link layer and physical layer devices in a 10-Gigabit Ethernet system.

SP9760

Abstract: ND350
Contextual Info: C ir ^ v SP9760 "C o 'p o io fio SIGNAL PROCESSING EXCELLENCE ULTRA HIGH SPEED 16-BIT ACCURATE, TRACK & HOLD AMPLIFIER FEATURES • 350 risec Acquisition Time to .005% for 20V step 250 risec Acquisition Time to .005% for 10V step ■ -94 dB Feedthrough Rejection Ratio 20V step

LM318 replacement

Abstract: PC318C UPC318 pc318
Contextual Info: N E C ELECTRONICS 6427525 N E C INC 01 DE^m SVSES OQlQOSi 5 8IC 10089 ELECTRONICS INC T-79-07- D. \ SEC A/PC318 HIGH-SPEED OPERATIONAL AM PLIFIER N E C Electronics Inc. Pin Configuration Description The/L/PC318 is a precision high-speed operational ampli­

chn 547

Abstract: CHN 829 chn 548 chn 734 CHN 549 JQC165FF TV19 R529 TISO58445 CHN 552
Contextual Info: 20~}00 .JQC165FF/ :<,5363+;<9/ 2312 87>/9 9/4+? 0DANOLDM V 59A mqcn]bcha ][j[\cfcns Fcf_ Ni2>E5778<5 V Ernl_g_fs fiq ]imn V 5 Filg A [h^ 5 Filg C ]ih`caol[ncihm V Sn[h^[l^ PCB f[sion Fcf_ Ni2>R6478456 V W[mb ncabn - `for jlii`_^ nsj_m [p[cf[\f_ V Ehpclihg_hn[f `lc_h^fs jli^o]n .RiHS ]igjfc[hn/

F799

Abstract: NL JH CHN 648 CHN 649
Contextual Info: 642+, >@097:7/?@=3 >75:/8 =38/C 4HERSPHQ Y M[r48B mqcn]bcha ][j[\cfcns Y Icab m_hmcncp_@ 7;6gW Y 7 Gilg D ]ih`caol[ncih Gcf_ Ni4@F799:>7 Y W[mb ncabn nsj_ [p[cf[\f_ Y Fhpclihg_hn[f `lc_h^fs jli^o]n /RiIS ]igjfc[hn0 Y Oonfch_ Ecg_hmcihm@ /784; r =4; r 76460 gg

nl 746

Abstract: CHN 642 CHN 848 cn/A/U 237 BG F799 78 mo 5 R48B CHN 647 GM 760
Contextual Info: 642+, >@097:7/?@=3 >75:/8 =38/C 4HERSPHQ Y M[r48B mqcn]bcha ][j[\cfcns Y Icab m_hmcncp_@ 7;6gW Y 7 Gilg D ]ih`caol[ncih Gcf_ Ni4@F799:>7 Y Pf[mnc] m_[f_^ nsj_ [p[cf[\f_ Y Fhpclihg_hn[f `lc_h^fs jli^o]n /RiIS ]igjfc[hn0 Y Oonfch_ Ecg_hmcihm@ /784; r =4; r 76460 gg

MDIO

Abstract: MDIO clause 45 MDIO clause 45 specification vhdl code for mac interface 10GBASE-X datasheets of optical fpgas giga media converter 10GBASE-LX4 UCF virtex-4 ffs 642
Contextual Info: XAUI v8.2 DS266 June 24, 2009 Product Specification Introduction LogiCORE IP Facts The LogiCORE IP XAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between data-link layer and physical layer devices in a 10-Gigabit Ethernet system.

Contextual Info: ANALOG DEVICES GSM 3 V Receiver IF Subsystem AD6458 FEATURES Fully Com pliant w ith Standard and Enhanced GSM Specification -1 2 dBm Input 1 dB Compression Point -2 dBm Input Third Order Intercept 10 dB SSB Noise Figure 330 SI D C-400 M Hz RF and LO Bandwidths

mc6821

Contextual Info: <s> MOTOROLA A d v an ce Inform ation 8-BIT MPU BUS-COMPATIBLE HIGH SPEED A-TO-D CONVERTER 8 -B IT M P U B U S -C O M P A T IB L E H IG H S P EED A -T O -D C O N V E R T E R The MC6108 is a m icrop ro cesso r co m p a tib le , 8-bit, high speed a na lo g -to -d ig ita l converter. Included are a precision reference,