FET MARKING G2 Search Results

3sk300

Abstract: DB64 DSA003642
Contextual Info: 3SK300 Silicon N Channel Dual Gate MOS FET UHF / VHF RF Amplifier ADE-208-449A Z 2nd. Edition Mar. 2001 Features • Low noise figure NF = 1.0 dB typ. at f = 200 MHz • High gain PG = 27.6 dB typ. at f = 200 MHz Outline MPAK-4 2 3 1 4 Note: Marking is “ZR–”

SLG55221

Abstract: fet n-channel pin configuration FET marking code
Contextual Info: 2 Rail GreenFETTM High Voltage Gate Driver Features Pin Configuration 5V Power supply • Drain Voltage Range 1.0V to 20V • • VCC • Controlled Turn on Slew Rate • TDFN-8 Package 2 4 3 8 7 6 5 PG G1/G2 S/DIS1 D 8-pin TDFN Top View Environmental Application Functions

SLG55221

Abstract: FET MARKING 600 V logic level fet fet MARKING g2 fet n-channel pin configuration
Contextual Info: 2 Rail GreenFETTM High Voltage Gate Driver Features Pin Configuration 5V Power supply • Drain Voltage Range 1.0V to 20V • • VCC • Controlled Turn on Slew Rate • TDFN-8 Package 2 4 3 8 7 6 5 PG G1/G2 S/DIS1 D 8-pin TDFN Top View Environmental Application Functions

IRF7907PBF

Contextual Info: IRF7907PbF-1 HEXFET Power MOSFET VDS 30 RDS on m ax Q1 V 16.4 (@VGS = 10V) mΩ RDS(on) m ax Q2 11.8 (@VGS = 10V) Qg (typical) Q1 6.7 Qg (typical) Q2 14 ID(@TA = 25°C)Q1 9.1 ID(@TA = 25°C)Q2 11 nC S2 1 8 D2 G2 2 7 D2 S1 3 6 D1 G1 4 5 D1 SO-8 A Applications

Contextual Info: IRF7904PbF-1 HEXFET Power MOSFET VDS 30 RDS on max Q1 V 16.2 (@VGS = 10V) mΩ RDS(on) max Q2 10.8 (@VGS = 10V) Qg (typical) Q1 7.5 Qg (typical) Q2 14 ID(@TA = 25°C)Q1 7.6 ID(@TA = 25°C)Q2 11 nC G1 1 8 D1 S2 2 7 S1 / D2 S2 3 6 S1 / D2 G2 4 5 S1 / D2 SO-8

IRF9910PBF

Contextual Info: IRF9910PbF-1 VDS 20 RDS on m ax Q1 HEXFET Power MOSFET V 13.4 (@VGS = 10V) mΩ RDS(on) m ax Q2 9.3 (@VGS = 10V) Qg (typical) Q1 7.4 Qg (typical) Q2 15 ID(@TA = 25°C)Q1 10 nC S2 1 8 D2 G2 2 7 D2 S1 3 6 D1 G1 4 5 D1 SO-8 A ID(@TA = 25°C)Q2 12 Applications

NEC uPA 63 H

Abstract: NEC uPA 63 NEC uPA 63 a NEC uPA 71 GL124 MEL12 UPA672T UPA572T UPA602 nec sc-59 fet
Contextual Info: DATA SHEET MOS FIELD EFFECT TRANSISTOR ,uPA502T N-CHANNEL MOS FET 5-PIN 2 CIRCUITS The pPA502T is a mini-mold device provided with two MOS FET circuits. It achieves high-density mounting and saves mounting costs. PACKAGE DIMENSIONS (in millimeters) 0.32 +O.’

TRANSISTOR SMD MARKING CODE s7

Abstract: marking code G7 SMD Transistor g3 smd transistor SMD Transistor G6 SMD Transistor Marking Code S7 g3 smd transistor view TRANSISTOR SMD MARKING CODE GFs fet diode date sheet FET MARKING CODE s5 smd transistor g3
Contextual Info: Philips Semiconductors Product specification N-channel enhancement mode TrenchMOS transistor array FEATURES PHN70308 SYMBOL • 30 mΩ isolation transistor • 80 mΩ spindle transistors • TrenchMOS technology • Logic level compatible • Surface mount package

Contextual Info: BG5412K Dual N-Channel MOSFET Tetrode • Designed for input stages of 2 band tuners 4 5 6 • Two AGC amplifiers in one single package, with on-chip internal switch 1 2 3 • Only one switching line to control both FETs • Integrated gate protection diodes

BCR108S

Abstract: BG5412K FET marking code
Contextual Info: BG5412K Dual N-Channel MOSFET Tetrode • Designed for input stages of 2 band tuners 4 5 6 • Two AGC amplifiers in one single package, with on-chip internal switch 1 2 3 • Only one switching line to control both FETs • Integrated gate protection diodes

200 Amp mosfet

Abstract: mosfet tetrode BCR108S BG5412K FET marking code
Contextual Info: BG5412K Dual N-Channel MOSFET Tetrode Preliminary • Designed for input stages of 2 band tuners 4 5 6 • Two AGC amplifiers in one single package, with on-chip internal switch 1 2 3 • Only one switching line to control both FETs • Integrated gate protection diodes

Contextual Info: UNISONIC TECHNOLOGIES CO., LTD L8200 Preliminary LINEAR INTEGRATED CIRCUIT CONFIDENTIAL, SUPPLIDE UNDE NDA SINGLE LNB-BIAS, CONTROL AND POWER MANAGEMENT SOLUTION  DESCRIPTION The UTC L8200 is a single chip power management and control solution for LNB’s. The highly integrate solution provides

91840E

Abstract: S/91840E
Contextual Info: LF PA K 56D BUK9K18-40E Dual N-channel TrenchMOS logic level FET 23 April 2013 Product data sheet 1. General description Dual logic level N-channel MOSFET in a LFPAK56D package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use

Contextual Info: LF PA K 56D BUK9K52-60E Dual N-channel TrenchMOS logic level FET 23 April 2013 Product data sheet 1. General description Dual logic level N-channel MOSFET in a LFPAK56D package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use

Contextual Info: LF PA K 56D BUK7K6R8-40E Dual N-channel TrenchMOS standard level FET 19 March 2013 Product data sheet 1. General description Dual standard level N-channel MOSFET in a LFPAK56D package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use

Contextual Info: LF PA K 56D BUK9K52-60E Dual N-channel TrenchMOS logic level FET 17 June 2013 Product data sheet 1. General description Dual logic level N-channel MOSFET in a LFPAK56D package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use

Contextual Info: LF PA K 56D BUK9K89-100E Dual N-channel TrenchMOS logic level FET 23 April 2013 Product data sheet 1. General description Dual logic level N-channel MOSFET in a LFPAK56D package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use

Contextual Info: LF PA K 56D BUK9K29-100E Dual N-channel TrenchMOS logic level FET 28 March 2013 Product data sheet 1. General description Dual logic level N-channel MOSFET in a LFPAK56D package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use

BF1009SR

Contextual Info: BF1009SR Dual - MOS FET Monolithic Integrated Circuit
For low noise, high gain controlled input stages up to 1GHz
Operating voltage 9V
Integrated stabilized bias network Drain AGC HF Input G2 G1 HF Output + DC GND EHA07215 ESD: Electrostatic discharge sensitive device, observe handling precaution!

BF1005R

Contextual Info: BF1005R Dual - MOS FET Monolithic Integrated Circuit
For low noise, high gain controlled input stages up to 1GHz
Operating voltage 5V
Integrated stabilized bias network Drain AGC HF Input G2 G1 HF Output + DC GND EHA07215 ESD: Electrostatic discharge sensitive device, observe handling precaution!

Contextual Info: LF PA K 56D BUK7K5R1-30E Dual N-channel TrenchMOS standard level FET 19 April 2013 Product data sheet 1. General description Dual standard level N-channel MOSFET in a LFPAK56D package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use

LFPAK56D

Abstract: BUK9K35-60E defect ppm
Contextual Info: LF PA K 56D BUK9K35-60E Dual N-channel TrenchMOS logic level FET 23 April 2013 Product data sheet 1. General description Dual logic level N-channel MOSFET in a LFPAK56D package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use

72540E

Contextual Info: LF PA K 56D BUK7K25-40E Dual N-channel TrenchMOS standard level FET 23 April 2013 Product data sheet 1. General description Dual standard level N-channel MOSFET in a LFPAK56D package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use

BF1005SR

Abstract: marking NZs
Contextual Info: BF1005SR Dual - MOS FET Monolithic Integrated Circuit
For low noise, high gain controlled input stages up to 1GHz
Operating voltage 5V
Integrated stabilized bias network Drain AGC HF Input G2 G1 HF Output + DC GND EHA07215 ESD: Electrostatic discharge sensitive device, observe handling precaution!